ARM: dts: rockchip: add vpu nodes for RK3066 and RK3188

Add the vpu node to the common rk3xxx.dtsi and only the powerdomain
property to the SoC specific device trees.

Signed-off-by: Alex Bee <knaerzche@gmail.com>
Link: https://lore.kernel.org/r/20210527154455.358869-12-knaerzche@gmail.com
Signed-off-by: Heiko Stuebner <heiko@sntech.de>

diff --git a/arch/arm/boot/dts/rk3066a.dtsi b/arch/arm/boot/dts/rk3066a.dtsi
index b15cbbe23ffc578bfd437c26cd57da8aae6fc19d..f5a665b5d209ff711320aaf2101bf847107eade8 100644 (file)
--- a/arch/arm/boot/dts/rk3066a.dtsi
+++ b/arch/arm/boot/dts/rk3066a.dtsi
@@ -868,6 +868,10 @@
        pinctrl-0 = <&uart3_xfer>;
 };
 
+&vpu {
+       power-domains = <&power RK3066_PD_VIDEO>;
+};
+
 &wdt {
        compatible = "rockchip,rk3066-wdt", "snps,dw-wdt";
 };

diff --git a/arch/arm/boot/dts/rk3188.dtsi b/arch/arm/boot/dts/rk3188.dtsi
index b36fcdd9a516024d79ab47e3952a4e8904e60f0c..793a1b9117fea5012b36e77270efde6873b0a674 100644 (file)
--- a/arch/arm/boot/dts/rk3188.dtsi
+++ b/arch/arm/boot/dts/rk3188.dtsi
@@ -801,6 +801,11 @@
        pinctrl-0 = <&uart3_xfer>;
 };
 
+&vpu {
+       compatible = "rockchip,rk3188-vpu", "rockchip,rk3066-vpu";
+       power-domains = <&power RK3188_PD_VIDEO>;
+};
+
 &wdt {
        compatible = "rockchip,rk3188-wdt", "snps,dw-wdt";
 };

diff --git a/arch/arm/boot/dts/rk3xxx.dtsi b/arch/arm/boot/dts/rk3xxx.dtsi
index f9bbc242444486da32c731ec85957af004b3236d..616a828e0c6e4c6f58588798d0c019767e0754a1 100644 (file)
--- a/arch/arm/boot/dts/rk3xxx.dtsi
+++ b/arch/arm/boot/dts/rk3xxx.dtsi
@@ -47,6 +47,18 @@
                status = "disabled";
        };
 
+       vpu: video-codec@10104000 {
+               compatible = "rockchip,rk3066-vpu";
+               reg = <0x10104000 0x800>;
+               interrupts = <GIC_SPI  9 IRQ_TYPE_LEVEL_HIGH>,
+                            <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
+               interrupt-names = "vepu", "vdpu";
+               clocks = <&cru ACLK_VDPU>, <&cru HCLK_VDPU>,
+                        <&cru ACLK_VEPU>, <&cru HCLK_VEPU>;
+               clock-names = "aclk_vdpu", "hclk_vdpu",
+                             "aclk_vepu", "hclk_vepu";
+       };
+
        L2: cache-controller@10138000 {
                compatible = "arm,pl310-cache";
                reg = <0x10138000 0x1000>;