drm/amd/display: correct static screen event mask
authorAllen Pan <allen.pan@amd.com>
Tue, 23 Jan 2024 20:14:40 +0000 (15:14 -0500)
committerAlex Deucher <alexander.deucher@amd.com>
Wed, 7 Feb 2024 17:26:22 +0000 (12:26 -0500)
[Why]
Hardware register definition changed

Reviewed-by: Charlene Liu <charlene.liu@amd.com>
Acked-by: Hamza Mahfooz <hamza.mahfooz@amd.com>
Signed-off-by: Allen Pan <allen.pan@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c
drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.h
drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_init.c
drivers/gpu/drm/amd/display/dc/hwss/dcn351/dcn351_init.c

index 8b6c49622f3b63c8e6dae68c507e1e45c5a736a2..4b92df23ff0db90498e722c0df0d8bbb149e76e2 100644 (file)
@@ -1342,8 +1342,8 @@ void dcn35_set_drr(struct pipe_ctx **pipe_ctx,
 {
        int i = 0;
        struct drr_params params = {0};
-       // DRR set trigger event mapped to OTG_TRIG_A (bit 11) for manual control flow
-       unsigned int event_triggers = 0x800;
+       // DRR set trigger event mapped to OTG_TRIG_A
+       unsigned int event_triggers = 0x2;//Bit[1]: OTG_TRIG_A
        // Note DRR trigger events are generated regardless of whether num frames met.
        unsigned int num_frames = 2;
 
@@ -1377,3 +1377,20 @@ void dcn35_set_drr(struct pipe_ctx **pipe_ctx,
                }
        }
 }
+void dcn35_set_static_screen_control(struct pipe_ctx **pipe_ctx,
+               int num_pipes, const struct dc_static_screen_params *params)
+{
+       unsigned int i;
+       unsigned int triggers = 0;
+
+       if (params->triggers.surface_update)
+               triggers |= 0x200;/*bit 9  : 10 0000 0000*/
+       if (params->triggers.cursor_update)
+               triggers |= 0x8;/*bit3*/
+       if (params->triggers.force_trigger)
+               triggers |= 0x1;
+       for (i = 0; i < num_pipes; i++)
+               pipe_ctx[i]->stream_res.tg->funcs->
+                       set_static_screen_control(pipe_ctx[i]->stream_res.tg,
+                                       triggers, params->num_frames);
+}
index fd66316e33de367da8c90e3520087fce385ebb5b..c354efa6c1b2f8f6e69754553f8ac905ffab8936 100644 (file)
@@ -90,4 +90,7 @@ uint32_t dcn35_get_idle_state(const struct dc *dc);
 void dcn35_set_drr(struct pipe_ctx **pipe_ctx,
                int num_pipes, struct dc_crtc_timing_adjust adjust);
 
+void dcn35_set_static_screen_control(struct pipe_ctx **pipe_ctx,
+               int num_pipes, const struct dc_static_screen_params *params);
+
 #endif /* __DC_HWSS_DCN35_H__ */
index 29a93dbc6631d923ad189e0ea1e7a609a7c08187..a93073055e7bfc976f6c9c4a2885a773a26ccf24 100644 (file)
@@ -70,7 +70,7 @@ static const struct hw_sequencer_funcs dcn35_funcs = {
        .update_bandwidth = dcn20_update_bandwidth,
        .set_drr = dcn35_set_drr,
        .get_position = dcn10_get_position,
-       .set_static_screen_control = dcn31_set_static_screen_control,
+       .set_static_screen_control = dcn35_set_static_screen_control,
        .setup_stereo = dcn10_setup_stereo,
        .set_avmute = dcn30_set_avmute,
        .log_hw_state = dcn10_log_hw_state,
index e5cb7fb8b2d4349a605d9d058e2ba31799bcc5d5..ab17fa1c64e8c5b405ae2f24a93c1ee54abefe10 100644 (file)
@@ -69,7 +69,7 @@ static const struct hw_sequencer_funcs dcn351_funcs = {
        .update_bandwidth = dcn20_update_bandwidth,
        .set_drr = dcn10_set_drr,
        .get_position = dcn10_get_position,
-       .set_static_screen_control = dcn31_set_static_screen_control,
+       .set_static_screen_control = dcn35_set_static_screen_control,
        .setup_stereo = dcn10_setup_stereo,
        .set_avmute = dcn30_set_avmute,
        .log_hw_state = dcn10_log_hw_state,