phy: qcom: edp: Add v6 specific ops and X1E80100 platform support

Add v6 HW support by implementing the version ops. Add the X1E80100
compatible and match config as it is v6.

Signed-off-by: Abel Vesa <abel.vesa@linaro.org>
Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Link: https://lore.kernel.org/r/20240221-phy-qualcomm-edp-x1e80100-v4-3-4e5018877bee@linaro.org
Signed-off-by: Vinod Koul <vkoul@kernel.org>

diff --git a/drivers/phy/qualcomm/phy-qcom-edp.c b/drivers/phy/qualcomm/phy-qcom-edp.c
index 9bbf977c7b4ed19eed8571a0f6cfce581965f53a..da2b32fb5b451110d6e6cb9c126e5c176a87ef81 100644 (file)
--- a/drivers/phy/qualcomm/phy-qcom-edp.c
+++ b/drivers/phy/qualcomm/phy-qcom-edp.c
@@ -24,6 +24,7 @@
 
 #include "phy-qcom-qmp-dp-phy.h"
 #include "phy-qcom-qmp-qserdes-com-v4.h"
+#include "phy-qcom-qmp-qserdes-com-v6.h"
 
 /* EDP_PHY registers */
 #define DP_PHY_CFG                              0x0010
@@ -532,6 +533,184 @@ static const struct qcom_edp_phy_cfg sc8280xp_edp_phy_cfg = {
        .ver_ops = &qcom_edp_phy_ops_v4,
 };
 
+static int qcom_edp_phy_power_on_v6(const struct qcom_edp *edp)
+{
+       u32 val;
+
+       writel(DP_PHY_PD_CTL_PWRDN | DP_PHY_PD_CTL_AUX_PWRDN |
+              DP_PHY_PD_CTL_LANE_0_1_PWRDN | DP_PHY_PD_CTL_LANE_2_3_PWRDN |
+              DP_PHY_PD_CTL_PLL_PWRDN | DP_PHY_PD_CTL_DP_CLAMP_EN,
+              edp->edp + DP_PHY_PD_CTL);
+       writel(0xfc, edp->edp + DP_PHY_MODE);
+
+       return readl_poll_timeout(edp->pll + QSERDES_V6_COM_CMN_STATUS,
+                                    val, val & BIT(7), 5, 200);
+}
+
+static int qcom_edp_phy_com_resetsm_cntrl_v6(const struct qcom_edp *edp)
+{
+       u32 val;
+
+       writel(0x20, edp->pll + QSERDES_V6_COM_RESETSM_CNTRL);
+
+       return readl_poll_timeout(edp->pll + QSERDES_V6_COM_C_READY_STATUS,
+                                    val, val & BIT(0), 500, 10000);
+}
+
+static int qcom_edp_com_bias_en_clkbuflr_v6(const struct qcom_edp *edp)
+{
+       /* Turn on BIAS current for PHY/PLL */
+       writel(0x1f, edp->pll + QSERDES_V6_COM_PLL_BIAS_EN_CLK_BUFLR_EN);
+
+       return 0;
+}
+
+static int qcom_edp_com_configure_ssc_v6(const struct qcom_edp *edp)
+{
+       const struct phy_configure_opts_dp *dp_opts = &edp->dp_opts;
+       u32 step1;
+       u32 step2;
+
+       switch (dp_opts->link_rate) {
+       case 1620:
+       case 2700:
+       case 8100:
+               step1 = 0x92;
+               step2 = 0x01;
+               break;
+
+       case 5400:
+               step1 = 0x18;
+               step2 = 0x02;
+               break;
+
+       default:
+               /* Other link rates aren't supported */
+               return -EINVAL;
+       }
+
+       writel(0x01, edp->pll + QSERDES_V6_COM_SSC_EN_CENTER);
+       writel(0x00, edp->pll + QSERDES_V6_COM_SSC_ADJ_PER1);
+       writel(0x36, edp->pll + QSERDES_V6_COM_SSC_PER1);
+       writel(0x01, edp->pll + QSERDES_V6_COM_SSC_PER2);
+       writel(step1, edp->pll + QSERDES_V6_COM_SSC_STEP_SIZE1_MODE0);
+       writel(step2, edp->pll + QSERDES_V6_COM_SSC_STEP_SIZE2_MODE0);
+
+       return 0;
+}
+
+static int qcom_edp_com_configure_pll_v6(const struct qcom_edp *edp)
+{
+       const struct phy_configure_opts_dp *dp_opts = &edp->dp_opts;
+       u32 div_frac_start2_mode0;
+       u32 div_frac_start3_mode0;
+       u32 dec_start_mode0;
+       u32 lock_cmp1_mode0;
+       u32 lock_cmp2_mode0;
+       u32 code1_mode0;
+       u32 code2_mode0;
+       u32 hsclk_sel;
+
+       switch (dp_opts->link_rate) {
+       case 1620:
+               hsclk_sel = 0x5;
+               dec_start_mode0 = 0x34;
+               div_frac_start2_mode0 = 0xc0;
+               div_frac_start3_mode0 = 0x0b;
+               lock_cmp1_mode0 = 0x37;
+               lock_cmp2_mode0 = 0x04;
+               code1_mode0 = 0x71;
+               code2_mode0 = 0x0c;
+               break;
+
+       case 2700:
+               hsclk_sel = 0x3;
+               dec_start_mode0 = 0x34;
+               div_frac_start2_mode0 = 0xc0;
+               div_frac_start3_mode0 = 0x0b;
+               lock_cmp1_mode0 = 0x07;
+               lock_cmp2_mode0 = 0x07;
+               code1_mode0 = 0x71;
+               code2_mode0 = 0x0c;
+               break;
+
+       case 5400:
+               hsclk_sel = 0x1;
+               dec_start_mode0 = 0x46;
+               div_frac_start2_mode0 = 0x00;
+               div_frac_start3_mode0 = 0x05;
+               lock_cmp1_mode0 = 0x0f;
+               lock_cmp2_mode0 = 0x0e;
+               code1_mode0 = 0x97;
+               code2_mode0 = 0x10;
+               break;
+
+       case 8100:
+               hsclk_sel = 0x0;
+               dec_start_mode0 = 0x34;
+               div_frac_start2_mode0 = 0xc0;
+               div_frac_start3_mode0 = 0x0b;
+               lock_cmp1_mode0 = 0x17;
+               lock_cmp2_mode0 = 0x15;
+               code1_mode0 = 0x71;
+               code2_mode0 = 0x0c;
+               break;
+
+       default:
+               /* Other link rates aren't supported */
+               return -EINVAL;
+       }
+
+       writel(0x01, edp->pll + QSERDES_V6_COM_SVS_MODE_CLK_SEL);
+       writel(0x0b, edp->pll + QSERDES_V6_COM_SYSCLK_EN_SEL);
+       writel(0x02, edp->pll + QSERDES_V6_COM_SYS_CLK_CTRL);
+       writel(0x0c, edp->pll + QSERDES_V6_COM_CLK_ENABLE1);
+       writel(0x06, edp->pll + QSERDES_V6_COM_SYSCLK_BUF_ENABLE);
+       writel(0x30, edp->pll + QSERDES_V6_COM_CLK_SELECT);
+       writel(hsclk_sel, edp->pll + QSERDES_V6_COM_HSCLK_SEL_1);
+       writel(0x07, edp->pll + QSERDES_V6_COM_PLL_IVCO);
+       writel(0x08, edp->pll + QSERDES_V6_COM_LOCK_CMP_EN);
+       writel(0x36, edp->pll + QSERDES_V6_COM_PLL_CCTRL_MODE0);
+       writel(0x16, edp->pll + QSERDES_V6_COM_PLL_RCTRL_MODE0);
+       writel(0x06, edp->pll + QSERDES_V6_COM_CP_CTRL_MODE0);
+       writel(dec_start_mode0, edp->pll + QSERDES_V6_COM_DEC_START_MODE0);
+       writel(0x00, edp->pll + QSERDES_V6_COM_DIV_FRAC_START1_MODE0);
+       writel(div_frac_start2_mode0, edp->pll + QSERDES_V6_COM_DIV_FRAC_START2_MODE0);
+       writel(div_frac_start3_mode0, edp->pll + QSERDES_V6_COM_DIV_FRAC_START3_MODE0);
+       writel(0x12, edp->pll + QSERDES_V6_COM_CMN_CONFIG_1);
+       writel(0x3f, edp->pll + QSERDES_V6_COM_INTEGLOOP_GAIN0_MODE0);
+       writel(0x00, edp->pll + QSERDES_V6_COM_INTEGLOOP_GAIN1_MODE0);
+       writel(0x00, edp->pll + QSERDES_V6_COM_VCO_TUNE_MAP);
+       writel(lock_cmp1_mode0, edp->pll + QSERDES_V6_COM_LOCK_CMP1_MODE0);
+       writel(lock_cmp2_mode0, edp->pll + QSERDES_V6_COM_LOCK_CMP2_MODE0);
+
+       writel(0x0a, edp->pll + QSERDES_V6_COM_BG_TIMER);
+       writel(0x14, edp->pll + QSERDES_V6_COM_PLL_CORE_CLK_DIV_MODE0);
+       writel(0x00, edp->pll + QSERDES_V6_COM_VCO_TUNE_CTRL);
+       writel(0x1f, edp->pll + QSERDES_V6_COM_PLL_BIAS_EN_CLK_BUFLR_EN);
+       writel(0x0f, edp->pll + QSERDES_V6_COM_CORE_CLK_EN);
+       writel(0xa0, edp->pll + QSERDES_V6_COM_VCO_TUNE1_MODE0);
+       writel(0x03, edp->pll + QSERDES_V6_COM_VCO_TUNE2_MODE0);
+
+       writel(code1_mode0, edp->pll + QSERDES_V6_COM_BIN_VCOCAL_CMP_CODE1_MODE0);
+       writel(code2_mode0, edp->pll + QSERDES_V6_COM_BIN_VCOCAL_CMP_CODE2_MODE0);
+
+       return 0;
+}
+
+static const struct phy_ver_ops qcom_edp_phy_ops_v6 = {
+       .com_power_on           = qcom_edp_phy_power_on_v6,
+       .com_resetsm_cntrl      = qcom_edp_phy_com_resetsm_cntrl_v6,
+       .com_bias_en_clkbuflr   = qcom_edp_com_bias_en_clkbuflr_v6,
+       .com_configure_pll      = qcom_edp_com_configure_pll_v6,
+       .com_configure_ssc      = qcom_edp_com_configure_ssc_v6,
+};
+
+static struct qcom_edp_phy_cfg x1e80100_phy_cfg = {
+       .swing_pre_emph_cfg = &dp_phy_swing_pre_emph_cfg,
+       .ver_ops = &qcom_edp_phy_ops_v6,
+};
+
 static int qcom_edp_phy_power_on(struct phy *phy)
 {
        const struct qcom_edp *edp = phy_get_drvdata(phy);
@@ -933,6 +1112,7 @@ static const struct of_device_id qcom_edp_phy_match_table[] = {
        { .compatible = "qcom,sc8180x-edp-phy", .data = &sc7280_dp_phy_cfg, },
        { .compatible = "qcom,sc8280xp-dp-phy", .data = &sc8280xp_dp_phy_cfg, },
        { .compatible = "qcom,sc8280xp-edp-phy", .data = &sc8280xp_edp_phy_cfg, },
+       { .compatible = "qcom,x1e80100-dp-phy", .data = &x1e80100_phy_cfg, },
        { }
 };
 MODULE_DEVICE_TABLE(of, qcom_edp_phy_match_table);