clk: x86: Move clk-pmc-atom register defines to include/linux/platform_data/x86/pmc_a...
authorHans de Goede <hdegoede@redhat.com>
Tue, 5 Mar 2024 10:59:11 +0000 (11:59 +0100)
committerIlpo Järvinen <ilpo.jarvinen@linux.intel.com>
Tue, 12 Mar 2024 10:48:15 +0000 (12:48 +0200)
Move the register defines for the Atom (Bay Trail, Cherry Trail) PMC
clocks to include/linux/platform_data/x86/pmc_atom.h.

This is a preparation patch to extend the S0i3 readiness checks
in drivers/platform/x86/pmc_atom.c with checking that the PMC
clocks are off on suspend entry.

Note these are added to include/linux/platform_data/x86/pmc_atom.h rather
then to include/linux/platform_data/x86/clk-pmc-atom.h because the former
already has all the other Atom PMC register defines.

Reviewed-by: Ilpo Järvinen <ilpo.jarvinen@linux.intel.com>
Acked-by: Stephen Boyd <sboyd@kernel.org>
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Link: https://lore.kernel.org/r/20240305105915.76242-2-hdegoede@redhat.com
Signed-off-by: Ilpo Järvinen <ilpo.jarvinen@linux.intel.com>
drivers/clk/x86/clk-pmc-atom.c
include/linux/platform_data/x86/pmc_atom.h

index 2974dd0ec6f4d0162dfbeec2b814e94ada5b2035..5ec9255e33faf75d8915909099465e565b2ce937 100644 (file)
 #include <linux/err.h>
 #include <linux/io.h>
 #include <linux/platform_data/x86/clk-pmc-atom.h>
+#include <linux/platform_data/x86/pmc_atom.h>
 #include <linux/platform_device.h>
 #include <linux/slab.h>
 
 #define PLT_CLK_NAME_BASE      "pmc_plt_clk"
 
-#define PMC_CLK_CTL_OFFSET             0x60
-#define PMC_CLK_CTL_SIZE               4
-#define PMC_CLK_NUM                    6
-#define PMC_CLK_CTL_GATED_ON_D3                0x0
-#define PMC_CLK_CTL_FORCE_ON           0x1
-#define PMC_CLK_CTL_FORCE_OFF          0x2
-#define PMC_CLK_CTL_RESERVED           0x3
-#define PMC_MASK_CLK_CTL               GENMASK(1, 0)
-#define PMC_MASK_CLK_FREQ              BIT(2)
-#define PMC_CLK_FREQ_XTAL              (0 << 2)        /* 25 MHz */
-#define PMC_CLK_FREQ_PLL               (1 << 2)        /* 19.2 MHz */
-
 struct clk_plt_fixed {
        struct clk_hw *clk;
        struct clk_lookup *lookup;
index b8a701c77fd00cc2d983ad69cca9ebd5a66acee9..557622ef039041fa722006fb4b06d97b0082813b 100644 (file)
                                BIT_ORED_DEDICATED_IRQ_GPSC | \
                                BIT_SHARED_IRQ_GPSS)
 
+/* External clk generator settings */
+#define PMC_CLK_CTL_OFFSET             0x60
+#define PMC_CLK_CTL_SIZE               4
+#define PMC_CLK_NUM                    6
+#define PMC_CLK_CTL_GATED_ON_D3                0x0
+#define PMC_CLK_CTL_FORCE_ON           0x1
+#define PMC_CLK_CTL_FORCE_OFF          0x2
+#define PMC_CLK_CTL_RESERVED           0x3
+#define PMC_MASK_CLK_CTL               GENMASK(1, 0)
+#define PMC_MASK_CLK_FREQ              BIT(2)
+#define PMC_CLK_FREQ_XTAL              (0 << 2)        /* 25 MHz */
+#define PMC_CLK_FREQ_PLL               (1 << 2)        /* 19.2 MHz */
+
 /* The timers accumulate time spent in sleep state */
 #define        PMC_S0IR_TMR            0x80
 #define        PMC_S0I1_TMR            0x84