unsigned long gpio;
 
        for_each_set_bit(gpio, &irq_mask, 2)
-               generic_handle_irq(irq_find_mapping(chip->irq.domain,
-                       19 + gpio*24));
+               generic_handle_domain_irq(chip->irq.domain,
+                                         19 + gpio*24);
 
        raw_spin_lock(&dio48egpio->lock);
 
 
                for_each_set_bit(bit_num, &irq_mask, 8) {
                        gpio = bit_num + boundary * 8;
 
-                       generic_handle_irq(irq_find_mapping(chip->irq.domain,
-                               gpio));
+                       generic_handle_domain_irq(chip->irq.domain,
+                                                 gpio);
                }
        }
 
 
        int gpio;
 
        for_each_set_bit(gpio, &idio16gpio->irq_mask, chip->ngpio)
-               generic_handle_irq(irq_find_mapping(chip->irq.domain, gpio));
+               generic_handle_domain_irq(chip->irq.domain, gpio);
 
        raw_spin_lock(&idio16gpio->lock);
 
 
              (readl(mm_gc->regs + ALTERA_GPIO_EDGE_CAP) &
              readl(mm_gc->regs + ALTERA_GPIO_IRQ_MASK)))) {
                writel(status, mm_gc->regs + ALTERA_GPIO_EDGE_CAP);
-               for_each_set_bit(i, &status, mm_gc->gc.ngpio) {
-                       generic_handle_irq(irq_find_mapping(irqdomain, i));
-               }
+               for_each_set_bit(i, &status, mm_gc->gc.ngpio)
+                       generic_handle_domain_irq(irqdomain, i);
        }
 
        chained_irq_exit(chip, desc);
        status = readl(mm_gc->regs + ALTERA_GPIO_DATA);
        status &= readl(mm_gc->regs + ALTERA_GPIO_IRQ_MASK);
 
-       for_each_set_bit(i, &status, mm_gc->gc.ngpio) {
-               generic_handle_irq(irq_find_mapping(irqdomain, i));
-       }
+       for_each_set_bit(i, &status, mm_gc->gc.ngpio)
+               generic_handle_domain_irq(irqdomain, i);
+
        chained_irq_exit(chip, desc);
 }
 
 
        struct gpio_chip *gc = irq_desc_get_handler_data(desc);
        struct irq_chip *ic = irq_desc_get_chip(desc);
        struct aspeed_sgpio *data = gpiochip_get_data(gc);
-       unsigned int i, p, girq;
+       unsigned int i, p;
        unsigned long reg;
 
        chained_irq_enter(ic, desc);
 
                reg = ioread32(bank_reg(data, bank, reg_irq_status));
 
-               for_each_set_bit(p, ®, 32) {
-                       girq = irq_find_mapping(gc->irq.domain, i * 32 + p);
-                       generic_handle_irq(girq);
-               }
-
+               for_each_set_bit(p, ®, 32)
+                       generic_handle_domain_irq(gc->irq.domain, i * 32 + p);
        }
 
        chained_irq_exit(ic, desc);
 
        struct gpio_chip *gc = irq_desc_get_handler_data(desc);
        struct irq_chip *ic = irq_desc_get_chip(desc);
        struct aspeed_gpio *data = gpiochip_get_data(gc);
-       unsigned int i, p, girq, banks;
+       unsigned int i, p, banks;
        unsigned long reg;
        struct aspeed_gpio *gpio = gpiochip_get_data(gc);
 
 
                reg = ioread32(bank_reg(data, bank, reg_irq_status));
 
-               for_each_set_bit(p, ®, 32) {
-                       girq = irq_find_mapping(gc->irq.domain, i * 32 + p);
-                       generic_handle_irq(girq);
-               }
-
+               for_each_set_bit(p, ®, 32)
+                       generic_handle_domain_irq(gc->irq.domain, i * 32 + p);
        }
 
        chained_irq_exit(ic, desc);
 
 
        raw_spin_unlock_irqrestore(&ctrl->lock, flags);
 
-       if (pending) {
-               for_each_set_bit(irq, &pending, gc->ngpio)
-                       generic_handle_irq(
-                               irq_linear_revmap(gc->irq.domain, irq));
-       }
+       for_each_set_bit(irq, &pending, gc->ngpio)
+               generic_handle_domain_irq(gc->irq.domain, irq);
 
        chained_irq_exit(irqchip, desc);
 }
 
                    (~(readl(reg_base + GPIO_INT_MASK(bank_id)))))) {
                for_each_set_bit(bit, &sta, 32) {
                        int hwirq = GPIO_PER_BANK * bank_id + bit;
-                       int child_irq =
-                               irq_find_mapping(bank->kona_gpio->irq_domain,
-                                                hwirq);
                        /*
                         * Clear interrupt before handler is called so we don't
                         * miss any interrupt occurred during executing them.
                        writel(readl(reg_base + GPIO_INT_STATUS(bank_id)) |
                               BIT(bit), reg_base + GPIO_INT_STATUS(bank_id));
                        /* Invoke interrupt handler */
-                       generic_handle_irq(child_irq);
+                       generic_handle_domain_irq(bank->kona_gpio->irq_domain,
+                                                 hwirq);
                }
        }
 
 
        unsigned long status;
 
        while ((status = brcmstb_gpio_get_active_irqs(bank))) {
-               unsigned int irq, offset;
+               unsigned int offset;
 
                for_each_set_bit(offset, &status, 32) {
                        if (offset >= bank->width)
                                dev_warn(&priv->pdev->dev,
                                         "IRQ for invalid GPIO (bank=%d, offset=%d)\n",
                                         bank->id, offset);
-                       irq = irq_linear_revmap(domain, hwbase + offset);
-                       generic_handle_irq(irq);
+                       generic_handle_domain_irq(domain, hwbase + offset);
                }
        }
 }
 
                ~ioread32(cgpio->regs + CDNS_GPIO_IRQ_MASK);
 
        for_each_set_bit(hwirq, &status, chip->ngpio)
-               generic_handle_irq(irq_find_mapping(chip->irq.domain, hwirq));
+               generic_handle_domain_irq(chip->irq.domain, hwirq);
 
        chained_irq_exit(irqchip, desc);
 }
 
                         */
                        hw_irq = (bank_num / 2) * 32 + bit;
 
-                       generic_handle_irq(
-                               irq_find_mapping(d->irq_domain, hw_irq));
+                       generic_handle_domain_irq(d->irq_domain, hw_irq);
                }
        }
        chained_irq_exit(irq_desc_get_chip(desc), desc);
 
 static void dln2_gpio_event(struct platform_device *pdev, u16 echo,
                            const void *data, int len)
 {
-       int pin, irq;
+       int pin, ret;
 
        const struct {
                __le16 count;
                return;
        }
 
-       irq = irq_find_mapping(dln2->gpio.irq.domain, pin);
-       if (!irq) {
-               dev_err(dln2->gpio.parent, "pin %d not mapped to IRQ\n", pin);
-               return;
-       }
-
        switch (dln2->irq_type[pin]) {
        case DLN2_GPIO_EVENT_CHANGE_RISING:
-               if (event->value)
-                       generic_handle_irq(irq);
+               if (!event->value)
+                       return;
                break;
        case DLN2_GPIO_EVENT_CHANGE_FALLING:
-               if (!event->value)
-                       generic_handle_irq(irq);
+               if (event->value)
+                       return;
                break;
-       default:
-               generic_handle_irq(irq);
        }
+
+       ret = generic_handle_domain_irq(dln2->gpio.irq.domain, pin);
+       if (unlikely(ret))
+               dev_err(dln2->gpio.parent, "pin %d not mapped to IRQ\n", pin);
 }
 
 static int dln2_gpio_probe(struct platform_device *pdev)
 
        while ((pending = em_gio_read(p, GIO_MST))) {
                offset = __ffs(pending);
                em_gio_write(p, GIO_IIR, BIT(offset));
-               generic_handle_irq(irq_find_mapping(p->irq_domain, offset));
+               generic_handle_domain_irq(p->irq_domain, offset);
                irqs_handled++;
        }
 
 
         */
        stat = readb(epg->base + EP93XX_GPIO_A_INT_STATUS);
        for_each_set_bit(offset, &stat, 8)
-               generic_handle_irq(irq_find_mapping(epg->gc[0].gc.irq.domain,
-                                                   offset));
+               generic_handle_domain_irq(epg->gc[0].gc.irq.domain,
+                                         offset);
 
        stat = readb(epg->base + EP93XX_GPIO_B_INT_STATUS);
        for_each_set_bit(offset, &stat, 8)
-               generic_handle_irq(irq_find_mapping(epg->gc[1].gc.irq.domain,
-                                                   offset));
+               generic_handle_domain_irq(epg->gc[1].gc.irq.domain,
+                                         offset);
 
        chained_irq_exit(irqchip, desc);
 }
 
        stat = readl(g->base + GPIO_INT_STAT_RAW);
        if (stat)
                for_each_set_bit(offset, &stat, gc->ngpio)
-                       generic_handle_irq(irq_find_mapping(gc->irq.domain,
-                                                           offset));
+                       generic_handle_domain_irq(gc->irq.domain, offset);
 
        chained_irq_exit(irqchip, desc);
 }
 
 
        chained_irq_enter(irq_c, desc);
        for_each_set_bit(hwirq, &irq_msk, HISI_GPIO_LINE_NUM_MAX)
-               generic_handle_irq(irq_find_mapping(hisi_gpio->chip.irq.domain,
-                                                   hwirq));
+               generic_handle_domain_irq(hisi_gpio->chip.irq.domain,
+                                         hwirq);
        chained_irq_exit(irq_c, desc);
 }
 
 
 
        chained_irq_enter(chip, desc);
 
-       for_each_set_bit(hwirq, &pending, 32) {
-               int irq = irq_find_mapping(hlwd->gpioc.irq.domain, hwirq);
-
-               generic_handle_irq(irq);
-       }
+       for_each_set_bit(hwirq, &pending, 32)
+               generic_handle_domain_irq(hlwd->gpioc.irq.domain, hwirq);
 
        chained_irq_exit(chip, desc);
 }
 
                /* Only interrupts that are enabled */
                pending &= enabled;
 
-               for_each_set_bit(gpio, &pending, 32) {
-                       unsigned int irq;
-
-                       irq = irq_find_mapping(gc->irq.domain, base + gpio);
-                       generic_handle_irq(irq);
-               }
+               for_each_set_bit(gpio, &pending, 32)
+                       generic_handle_domain_irq(gc->irq.domain, base + gpio);
        }
 
        chained_irq_exit(irqchip, desc);
 
        mask = gc->read_reg(mpc8xxx_gc->regs + GPIO_IER)
                & gc->read_reg(mpc8xxx_gc->regs + GPIO_IMR);
        for_each_set_bit(i, &mask, 32)
-               generic_handle_irq(irq_linear_revmap(mpc8xxx_gc->irq, 31 - i));
+               generic_handle_domain_irq(mpc8xxx_gc->irq, 31 - i);
 
        return IRQ_HANDLED;
 }
 
        pending = mtk_gpio_r32(rg, GPIO_REG_STAT);
 
        for_each_set_bit(bit, &pending, MTK_BANK_WIDTH) {
-               u32 map = irq_find_mapping(gc->irq.domain, bit);
-
-               generic_handle_irq(map);
+               generic_handle_domain_irq(gc->irq.domain, bit);
                mtk_gpio_w32(rg, GPIO_REG_STAT, BIT(bit));
                ret |= IRQ_HANDLED;
        }
 
                if (port->both_edges & (1 << irqoffset))
                        mxc_flip_edge(port, irqoffset);
 
-               generic_handle_irq(irq_find_mapping(port->domain, irqoffset));
+               generic_handle_domain_irq(port->domain, irqoffset);
 
                irq_stat &= ~(1 << irqoffset);
        }
 
                if (port->both_edges & (1 << irqoffset))
                        mxs_flip_edge(port, irqoffset);
 
-               generic_handle_irq(irq_find_mapping(port->domain, irqoffset));
+               generic_handle_domain_irq(port->domain, irqoffset);
                irq_stat &= ~(1 << irqoffset);
        }
 }
 
 
                        raw_spin_lock_irqsave(&bank->wa_lock, wa_lock_flags);
 
-                       generic_handle_irq(irq_find_mapping(bank->chip.irq.domain,
-                                                           bit));
+                       generic_handle_domain_irq(bank->chip.irq.domain, bit);
 
                        raw_spin_unlock_irqrestore(&bank->wa_lock,
                                                   wa_lock_flags);
 
                return IRQ_NONE;
 
        for_each_set_bit(gpio, &idio16gpio->irq_mask, chip->ngpio)
-               generic_handle_irq(irq_find_mapping(chip->irq.domain, gpio));
+               generic_handle_domain_irq(chip->irq.domain, gpio);
 
        raw_spin_lock(&idio16gpio->lock);
 
 
        irq_mask = idio24gpio->irq_mask & irq_status;
 
        for_each_set_bit(gpio, &irq_mask, chip->ngpio - 24)
-               generic_handle_irq(irq_find_mapping(chip->irq.domain,
-                       gpio + 24));
+               generic_handle_domain_irq(chip->irq.domain, gpio + 24);
 
        raw_spin_lock(&idio24gpio->lock);
 
 
        pending = readb(pl061->base + GPIOMIS);
        if (pending) {
                for_each_set_bit(offset, &pending, PL061_GPIO_NR)
-                       generic_handle_irq(irq_find_mapping(gc->irq.domain,
-                                                           offset));
+                       generic_handle_domain_irq(gc->irq.domain,
+                                                 offset);
        }
 
        chained_irq_exit(irqchip, desc);
 
                        for_each_set_bit(n, &gedr, BITS_PER_LONG) {
                                loop = 1;
 
-                               generic_handle_irq(
-                                       irq_find_mapping(pchip->irqdomain,
-                                                        gpio + n));
+                               generic_handle_domain_irq(pchip->irqdomain,
+                                                         gpio + n);
                        }
                }
                handled += loop;
        struct pxa_gpio_chip *pchip = d;
 
        if (in_irq == pchip->irq0) {
-               generic_handle_irq(irq_find_mapping(pchip->irqdomain, 0));
+               generic_handle_domain_irq(pchip->irqdomain, 0);
        } else if (in_irq == pchip->irq1) {
-               generic_handle_irq(irq_find_mapping(pchip->irqdomain, 1));
+               generic_handle_domain_irq(pchip->irqdomain, 1);
        } else {
                pr_err("%s() unknown irq %d\n", __func__, in_irq);
                return IRQ_NONE;
 
                          gpio_rcar_read(p, INTMSK))) {
                offset = __ffs(pending);
                gpio_rcar_write(p, INTCLR, BIT(offset));
-               generic_handle_irq(irq_find_mapping(p->gpio_chip.irq.domain,
-                                                   offset));
+               generic_handle_domain_irq(p->gpio_chip.irq.domain,
+                                         offset);
                irqs_handled++;
        }
 
 
        struct irq_chip *ic = irq_desc_get_chip(desc);
        struct rda_gpio *rda_gpio = gpiochip_get_data(chip);
        unsigned long status;
-       u32 n, girq;
+       u32 n;
 
        chained_irq_enter(ic, desc);
 
        /* Only lower 8 bits are capable of generating interrupts */
        status &= RDA_GPIO_IRQ_MASK;
 
-       for_each_set_bit(n, &status, RDA_GPIO_BANK_NR) {
-               girq = irq_find_mapping(chip->irq.domain, n);
-               generic_handle_irq(girq);
-       }
+       for_each_set_bit(n, &status, RDA_GPIO_BANK_NR)
+               generic_handle_domain_irq(chip->irq.domain, n);
 
        chained_irq_exit(ic, desc);
 }
 
        struct irq_chip *irq_chip = irq_desc_get_chip(desc);
        unsigned int lines_done;
        unsigned int port_pin_count;
-       unsigned int irq;
        unsigned long status;
        int offset;
 
        for (lines_done = 0; lines_done < gc->ngpio; lines_done += 8) {
                status = realtek_gpio_read_isr(ctrl, lines_done / 8);
                port_pin_count = min(gc->ngpio - lines_done, 8U);
-               for_each_set_bit(offset, &status, port_pin_count) {
-                       irq = irq_find_mapping(gc->irq.domain, offset);
-                       generic_handle_irq(irq);
-               }
+               for_each_set_bit(offset, &status, port_pin_count)
+                       generic_handle_domain_irq(gc->irq.domain, offset);
        }
 
        chained_irq_exit(irq_chip, desc);
 
 
        pending = (resume_status << sch->resume_base) | core_status;
        for_each_set_bit(offset, &pending, sch->chip.ngpio)
-               generic_handle_irq(irq_find_mapping(gc->irq.domain, offset));
+               generic_handle_domain_irq(gc->irq.domain, offset);
 
        /* Set returning value depending on whether we handled an interrupt */
        ret = pending ? ACPI_INTERRUPT_HANDLED : ACPI_INTERRUPT_NOT_HANDLED;
 
                return IRQ_NONE;
 
        for_each_set_bit(irq_bit, &irq_stat, 32)
-               generic_handle_irq(irq_find_mapping(sd->id, irq_bit));
+               generic_handle_domain_irq(sd->id, irq_bit);
 
        return IRQ_HANDLED;
 }
 
        struct gpio_chip *chip = irq_desc_get_handler_data(desc);
        struct irq_chip *ic = irq_desc_get_chip(desc);
        struct sprd_gpio *sprd_gpio = gpiochip_get_data(chip);
-       u32 bank, n, girq;
+       u32 bank, n;
 
        chained_irq_enter(ic, desc);
 
                unsigned long reg = readl_relaxed(base + SPRD_GPIO_MIS) &
                        SPRD_GPIO_BANK_MASK;
 
-               for_each_set_bit(n, ®, SPRD_GPIO_BANK_NR) {
-                       girq = irq_find_mapping(chip->irq.domain,
-                                               bank * SPRD_GPIO_BANK_NR + n);
-
-                       generic_handle_irq(girq);
-               }
-
+               for_each_set_bit(n, ®, SPRD_GPIO_BANK_NR)
+                       generic_handle_domain_irq(chip->irq.domain,
+                                                 bank * SPRD_GPIO_BANK_NR + n);
        }
        chained_irq_exit(ic, desc);
 }
 
        int i;
 
        for_each_set_bit(i, &bits, 32)
-               generic_handle_irq(irq_find_mapping(tb10x_gpio->domain, i));
+               generic_handle_domain_irq(tb10x_gpio->domain, i);
 
        return IRQ_HANDLED;
 }
 
                lvl = tegra_gpio_readl(tgi, GPIO_INT_LVL(tgi, gpio));
 
                for_each_set_bit(pin, &sta, 8) {
+                       int ret;
+
                        tegra_gpio_writel(tgi, 1 << pin,
                                          GPIO_INT_CLR(tgi, gpio));
 
                                chained_irq_exit(chip, desc);
                        }
 
-                       irq = irq_find_mapping(domain, gpio + pin);
-                       if (WARN_ON(irq == 0))
-                               continue;
-
-                       generic_handle_irq(irq);
+                       ret = generic_handle_domain_irq(domain, gpio + pin);
+                       WARN_RATELIMIT(ret, "hwirq = %d", gpio + pin);
                }
        }
 
 
 
        for (i = 0; i < gpio->soc->num_ports; i++) {
                const struct tegra_gpio_port *port = &gpio->soc->ports[i];
-               unsigned int pin, irq;
+               unsigned int pin;
                unsigned long value;
                void __iomem *base;
 
                value = readl(base + TEGRA186_GPIO_INTERRUPT_STATUS(1));
 
                for_each_set_bit(pin, &value, port->pins) {
-                       irq = irq_find_mapping(domain, offset + pin);
-                       if (WARN_ON(irq == 0))
-                               continue;
-
-                       generic_handle_irq(irq);
+                       int ret = generic_handle_domain_irq(domain, offset + pin);
+                       WARN_RATELIMIT(ret, "hwirq = %d", offset + pin);
                }
 
 skip:
 
        struct tqmx86_gpio_data *gpio = gpiochip_get_data(chip);
        struct irq_chip *irq_chip = irq_desc_get_chip(desc);
        unsigned long irq_bits;
-       int i = 0, child_irq;
+       int i = 0;
        u8 irq_status;
 
        chained_irq_enter(irq_chip, desc);
        tqmx86_gpio_write(gpio, irq_status, TQMX86_GPIIS);
 
        irq_bits = irq_status;
-       for_each_set_bit(i, &irq_bits, TQMX86_NGPI) {
-               child_irq = irq_find_mapping(gpio->chip.irq.domain,
-                                            i + TQMX86_NGPO);
-               generic_handle_irq(child_irq);
-       }
+       for_each_set_bit(i, &irq_bits, TQMX86_NGPI)
+               generic_handle_domain_irq(gpio->chip.irq.domain,
+                                         i + TQMX86_NGPO);
 
        chained_irq_exit(irq_chip, desc);
 }
 
        for_each_set_bit(pin, &irq_isfr, VF610_GPIO_PER_PORT) {
                vf610_gpio_writel(BIT(pin), port->base + PORT_ISFR);
 
-               generic_handle_irq(irq_find_mapping(port->gc.irq.domain, pin));
+               generic_handle_domain_irq(port->gc.irq.domain, pin);
        }
 
        chained_irq_exit(chip, desc);
 
                for_each_set_bit(port, &int_pending, 3) {
                        int_id = inb(ws16c48gpio->base + 8 + port);
                        for_each_set_bit(gpio, &int_id, 8)
-                               generic_handle_irq(irq_find_mapping(
-                                       chip->irq.domain, gpio + 8*port));
+                               generic_handle_domain_irq(chip->irq.domain,
+                                                         gpio + 8*port);
                }
 
                int_pending = inb(ws16c48gpio->base + 6) & 0x7;
 
                int_bits = level | event;
 
                for_each_set_bit(bit, &int_bits, gc->ngpio)
-                       generic_handle_irq(irq_linear_revmap(gc->irq.domain, bit));
+                       generic_handle_domain_irq(gc->irq.domain, bit);
        }
 
        return int_bits ? IRQ_HANDLED : IRQ_NONE;
 
 
        for_each_set_bit(bit, all, 64) {
                irq_offset = xgpio_from_bit(chip, bit);
-               generic_handle_irq(irq_find_mapping(gc->irq.domain, irq_offset));
+               generic_handle_domain_irq(gc->irq.domain, irq_offset);
        }
 
        chained_irq_exit(irqchip, desc);
 
                }
 
                if (gpio_stat & BIT(gpio % XLP_GPIO_REGSZ))
-                       generic_handle_irq(irq_find_mapping(
-                                               priv->chip.irq.domain, gpio));
+                       generic_handle_domain_irq(priv->chip.irq.domain, gpio);
        }
        chained_irq_exit(irqchip, desc);
 }
 
        if (!pending)
                return;
 
-       for_each_set_bit(offset, &pending, 32) {
-               unsigned int gpio_irq;
-
-               gpio_irq = irq_find_mapping(irqdomain, offset + bank_offset);
-               generic_handle_irq(gpio_irq);
-       }
+       for_each_set_bit(offset, &pending, 32)
+               generic_handle_domain_irq(irqdomain, offset + bank_offset);
 }
 
 /**