drm/i915: Fix cs timestamp frequency for cl/bw

Despite what the spec says the TIMESTAMP register seems to
tick once every hrawclk (confirmed on i965gm and g35).

v2: Rebase

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20221031135703.14670-4-ville.syrjala@linux.intel.com
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>

diff --git a/drivers/gpu/drm/i915/gt/intel_gt_clock_utils.c b/drivers/gpu/drm/i915/gt/intel_gt_clock_utils.c
index 23a27e49b8983444aa2c6bd51186acd34a648678..2a6a4ca7fdad6de759b5abb5adf78d62a1a5baa7 100644 (file)
--- a/drivers/gpu/drm/i915/gt/intel_gt_clock_utils.c
+++ b/drivers/gpu/drm/i915/gt/intel_gt_clock_utils.c
@@ -147,8 +147,10 @@ static u32 gen4_read_clock_frequency(struct intel_uncore *uncore)
         *     "The value in this register increments once every 16
         *      hclks." (through the “Clocking Configuration”
         *      (“CLKCFG”) MCHBAR register)
+        *
+        * Testing on actual hardware has shown there is no /16.
         */
-       return RUNTIME_INFO(uncore->i915)->rawclk_freq * 1000 / 16;
+       return RUNTIME_INFO(uncore->i915)->rawclk_freq * 1000;
 }
 
 static u32 read_clock_frequency(struct intel_uncore *uncore)