dt-bindings: clock: google,gs101-clock: add HSI0 clock management unit

Add dt-schema documentation and clock IDs for the high speed interface
0 HSI0 clock management unit. This is used (amongst others) for USB.

While the usual (sed) script has been used to derive the linux clock
IDs from the data sheet, one manual tweak was applied to fix a typo
which we don't want to carry:
    HSI0_USPDPDBG_USER -> HSI0_USBDPDBG_USER (note USB vs USP).

Signed-off-by: André Draszik <andre.draszik@linaro.org>
Reviewed-by: Rob Herring (Arm) <robh@kernel.org>
Link: https://lore.kernel.org/r/20240423-hsi0-gs101-v1-1-2c3ddb50c720@linaro.org
Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>

diff --git a/Documentation/devicetree/bindings/clock/google,gs101-clock.yaml b/Documentation/devicetree/bindings/clock/google,gs101-clock.yaml
index 1d2bcea41c8588b0dbe10c6c870e3d75f09b220b..94dcc4f84c8597535a2d2d17289bb0786cd5bb18 100644 (file)
--- a/Documentation/devicetree/bindings/clock/google,gs101-clock.yaml
+++ b/Documentation/devicetree/bindings/clock/google,gs101-clock.yaml
@@ -30,16 +30,17 @@ properties:
       - google,gs101-cmu-top
       - google,gs101-cmu-apm
       - google,gs101-cmu-misc
+      - google,gs101-cmu-hsi0
       - google,gs101-cmu-peric0
       - google,gs101-cmu-peric1
 
   clocks:
     minItems: 1
-    maxItems: 3
+    maxItems: 5
 
   clock-names:
     minItems: 1
-    maxItems: 3
+    maxItems: 5
 
   "#clock-cells":
     const: 1
@@ -72,6 +73,30 @@ allOf:
           items:
             - const: oscclk
 
+  - if:
+      properties:
+        compatible:
+          contains:
+            const: google,gs101-cmu-hsi0
+
+    then:
+      properties:
+        clocks:
+          items:
+            - description: External reference clock (24.576 MHz)
+            - description: HSI0 bus clock (from CMU_TOP)
+            - description: DPGTC (from CMU_TOP)
+            - description: USB DRD controller clock (from CMU_TOP)
+            - description: USB Display Port debug clock (from CMU_TOP)
+
+        clock-names:
+          items:
+            - const: oscclk
+            - const: bus
+            - const: dpgtc
+            - const: usb31drd
+            - const: usbdpdbg
+
   - if:
       properties:
         compatible:

diff --git a/include/dt-bindings/clock/google,gs101.h b/include/dt-bindings/clock/google,gs101.h
index 3dac3577788a70af3b5c80a0ea5b599559e53c59..7a2006f0edf14415c4c19d21f848b73ead31a89d 100644 (file)
--- a/include/dt-bindings/clock/google,gs101.h
+++ b/include/dt-bindings/clock/google,gs101.h
@@ -313,6 +313,60 @@
 #define CLK_APM_PLL_DIV4_APM                           70
 #define CLK_APM_PLL_DIV16_APM                          71
 
+/* CMU_HSI0 */
+#define CLK_FOUT_USB_PLL                                       1
+#define CLK_MOUT_PLL_USB                                       2
+#define CLK_MOUT_HSI0_ALT_USER                                 3
+#define CLK_MOUT_HSI0_BUS_USER                                 4
+#define CLK_MOUT_HSI0_DPGTC_USER                               5
+#define CLK_MOUT_HSI0_TCXO_USER                                        6
+#define CLK_MOUT_HSI0_USB20_USER                               7
+#define CLK_MOUT_HSI0_USB31DRD_USER                            8
+#define CLK_MOUT_HSI0_USBDPDBG_USER                            9
+#define CLK_MOUT_HSI0_BUS                                      10
+#define CLK_MOUT_HSI0_USB20_REF                                        11
+#define CLK_MOUT_HSI0_USB31DRD                                 12
+#define CLK_DOUT_HSI0_USB31DRD                                 13
+#define CLK_GOUT_HSI0_PCLK                                     14
+#define CLK_GOUT_HSI0_USB31DRD_I_USB31DRD_SUSPEND_CLK_26       15
+#define CLK_GOUT_HSI0_CLK_HSI0_ALT                             16
+#define CLK_GOUT_HSI0_DP_LINK_I_DP_GTC_CLK                     17
+#define CLK_GOUT_HSI0_DP_LINK_I_PCLK                           18
+#define CLK_GOUT_HSI0_D_TZPC_HSI0_PCLK                         19
+#define CLK_GOUT_HSI0_ETR_MIU_I_ACLK                           20
+#define CLK_GOUT_HSI0_ETR_MIU_I_PCLK                           21
+#define CLK_GOUT_HSI0_GPC_HSI0_PCLK                            22
+#define CLK_GOUT_HSI0_LHM_AXI_G_ETR_HSI0_I_CLK                 23
+#define CLK_GOUT_HSI0_LHM_AXI_P_AOCHSI0_I_CLK                  24
+#define CLK_GOUT_HSI0_LHM_AXI_P_HSI0_I_CLK                     25
+#define CLK_GOUT_HSI0_LHS_ACEL_D_HSI0_I_CLK                    26
+#define CLK_GOUT_HSI0_LHS_AXI_D_HSI0AOC_I_CLK                  27
+#define CLK_GOUT_HSI0_PPMU_HSI0_AOC_ACLK                       28
+#define CLK_GOUT_HSI0_PPMU_HSI0_AOC_PCLK                       29
+#define CLK_GOUT_HSI0_PPMU_HSI0_BUS0_ACLK                      30
+#define CLK_GOUT_HSI0_PPMU_HSI0_BUS0_PCLK                      31
+#define CLK_GOUT_HSI0_CLK_HSI0_BUS_CLK                         32
+#define CLK_GOUT_HSI0_SSMT_USB_ACLK                            33
+#define CLK_GOUT_HSI0_SSMT_USB_PCLK                            34
+#define CLK_GOUT_HSI0_SYSMMU_USB_CLK_S2                                35
+#define CLK_GOUT_HSI0_SYSREG_HSI0_PCLK                         36
+#define CLK_GOUT_HSI0_UASC_HSI0_CTRL_ACLK                      37
+#define CLK_GOUT_HSI0_UASC_HSI0_CTRL_PCLK                      38
+#define CLK_GOUT_HSI0_UASC_HSI0_LINK_ACLK                      39
+#define CLK_GOUT_HSI0_UASC_HSI0_LINK_PCLK                      40
+#define CLK_GOUT_HSI0_USB31DRD_ACLK_PHYCTRL                    41
+#define CLK_GOUT_HSI0_USB31DRD_BUS_CLK_EARLY                   42
+#define CLK_GOUT_HSI0_USB31DRD_I_USB20_PHY_REFCLK_26           43
+#define CLK_GOUT_HSI0_USB31DRD_I_USB31DRD_REF_CLK_40           44
+#define CLK_GOUT_HSI0_USB31DRD_I_USBDPPHY_REF_SOC_PLL          45
+#define CLK_GOUT_HSI0_USB31DRD_I_USBDPPHY_SCL_APB_PCLK         46
+#define CLK_GOUT_HSI0_USB31DRD_I_USBPCS_APB_CLK                        47
+#define CLK_GOUT_HSI0_USB31DRD_USBDPPHY_I_ACLK                 48
+#define CLK_GOUT_HSI0_USB31DRD_USBDPPHY_UDBG_I_APB_PCLK                49
+#define CLK_GOUT_HSI0_XIU_D0_HSI0_ACLK                         50
+#define CLK_GOUT_HSI0_XIU_D1_HSI0_ACLK                         51
+#define CLK_GOUT_HSI0_XIU_P_HSI0_ACLK                          52
+
 /* CMU_MISC */
 #define CLK_MOUT_MISC_BUS_USER                         1
 #define CLK_MOUT_MISC_SSS_USER                         2