arm64: dts: ti: k3-am64: Fix indentation in watchdog nodes

Use single instead of double tab.

Signed-off-by: Wadim Egorov <w.egorov@phytec.de>
Link: https://lore.kernel.org/r/20230912133036.257277-1-w.egorov@phytec.de
Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>

diff --git a/arch/arm64/boot/dts/ti/k3-am64-main.dtsi b/arch/arm64/boot/dts/ti/k3-am64-main.dtsi
index 1933c9dd1d9f3f3be0285553fc2afb34d91df009..2e50030d09ad4d522b2826e019b8acba225ebe5e 100644 (file)
--- a/arch/arm64/boot/dts/ti/k3-am64-main.dtsi
+++ b/arch/arm64/boot/dts/ti/k3-am64-main.dtsi
@@ -1169,21 +1169,21 @@
        };
 
        main_rti0: watchdog@e000000 {
-                       compatible = "ti,j7-rti-wdt";
-                       reg = <0x00 0xe000000 0x00 0x100>;
-                       clocks = <&k3_clks 125 0>;
-                       power-domains = <&k3_pds 125 TI_SCI_PD_EXCLUSIVE>;
-                       assigned-clocks = <&k3_clks 125 0>;
-                       assigned-clock-parents = <&k3_clks 125 2>;
+               compatible = "ti,j7-rti-wdt";
+               reg = <0x00 0xe000000 0x00 0x100>;
+               clocks = <&k3_clks 125 0>;
+               power-domains = <&k3_pds 125 TI_SCI_PD_EXCLUSIVE>;
+               assigned-clocks = <&k3_clks 125 0>;
+               assigned-clock-parents = <&k3_clks 125 2>;
        };
 
        main_rti1: watchdog@e010000 {
-                       compatible = "ti,j7-rti-wdt";
-                       reg = <0x00 0xe010000 0x00 0x100>;
-                       clocks = <&k3_clks 126 0>;
-                       power-domains = <&k3_pds 126 TI_SCI_PD_EXCLUSIVE>;
-                       assigned-clocks = <&k3_clks 126 0>;
-                       assigned-clock-parents = <&k3_clks 126 2>;
+               compatible = "ti,j7-rti-wdt";
+               reg = <0x00 0xe010000 0x00 0x100>;
+               clocks = <&k3_clks 126 0>;
+               power-domains = <&k3_pds 126 TI_SCI_PD_EXCLUSIVE>;
+               assigned-clocks = <&k3_clks 126 0>;
+               assigned-clock-parents = <&k3_clks 126 2>;
        };
 
        icssg0: icssg@30000000 {