arm64: tegra: Update AHUB clock parent and rate
authorSameer Pujar <spujar@nvidia.com>
Thu, 29 Jun 2023 05:12:17 +0000 (10:42 +0530)
committerThierry Reding <treding@nvidia.com>
Thu, 13 Jul 2023 15:13:25 +0000 (17:13 +0200)
I2S data sanity test failures are seen at lower AHUB clock rates
on Tegra234. The Tegra194 uses the same clock relationship for AHUB
and it is likely that similar issues would be seen. Thus update the
AHUB clock parent and rates here as well for Tegra194, Tegra186
and Tegra210.

Fixes: 177208f7b06d ("arm64: tegra: Add DT binding for AHUB components")
Cc: stable@vger.kernel.org
Signed-off-by: Sameer Pujar <spujar@nvidia.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>
arch/arm64/boot/dts/nvidia/tegra186.dtsi
arch/arm64/boot/dts/nvidia/tegra194.dtsi
arch/arm64/boot/dts/nvidia/tegra210.dtsi

index 7e4c496fd91ce8835e21311219e81babec9e4a4d..2b3bb5d0af17bd521f87db0484fcbe943dd1a797 100644 (file)
                        clocks = <&bpmp TEGRA186_CLK_AHUB>;
                        clock-names = "ahub";
                        assigned-clocks = <&bpmp TEGRA186_CLK_AHUB>;
-                       assigned-clock-parents = <&bpmp TEGRA186_CLK_PLL_A_OUT0>;
+                       assigned-clock-parents = <&bpmp TEGRA186_CLK_PLLP_OUT0>;
+                       assigned-clock-rates = <81600000>;
                        #address-cells = <1>;
                        #size-cells = <1>;
                        ranges = <0x02900800 0x02900800 0x11800>;
index 154fc8c0eb6d4d67667dd6a3f992f372754eb108..33f92b77cd9d9e530eae87a4bb8ba61993ceffeb 100644 (file)
                                clocks = <&bpmp TEGRA194_CLK_AHUB>;
                                clock-names = "ahub";
                                assigned-clocks = <&bpmp TEGRA194_CLK_AHUB>;
-                               assigned-clock-parents = <&bpmp TEGRA194_CLK_PLLA_OUT0>;
+                               assigned-clock-parents = <&bpmp TEGRA194_CLK_PLLP_OUT0>;
+                               assigned-clock-rates = <81600000>;
                                status = "disabled";
 
                                #address-cells = <2>;
index 617583ff273664eace4f055c58dff6d53e3ba3af..e7b4e30139645f82d14f4661392de39b8cf7d3f1 100644 (file)
                        clocks = <&tegra_car TEGRA210_CLK_D_AUDIO>;
                        clock-names = "ahub";
                        assigned-clocks = <&tegra_car TEGRA210_CLK_D_AUDIO>;
-                       assigned-clock-parents = <&tegra_car TEGRA210_CLK_PLL_A_OUT0>;
+                       assigned-clock-parents = <&tegra_car TEGRA210_CLK_PLL_P>;
+                       assigned-clock-rates = <81600000>;
                        #address-cells = <1>;
                        #size-cells = <1>;
                        ranges = <0x702d0000 0x702d0000 0x0000e400>;