u32 mode, val;
        u8 offset;
 
-       /* DAI clock polarity */
+       /*
+        * DAI clock polarity
+        *
+        * The setup for LRCK contradicts the datasheet, but under a
+        * scope it's clear that the LRCK polarity is reversed
+        * compared to the expected polarity on the bus.
+        */
        switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
        case SND_SOC_DAIFMT_IB_IF:
                /* Invert both clocks */
-               val = SUN8I_I2S_FMT0_BCLK_POLARITY_INVERTED |
-                     SUN8I_I2S_FMT0_LRCLK_POLARITY_INVERTED;
+               val = SUN8I_I2S_FMT0_BCLK_POLARITY_INVERTED;
                break;
        case SND_SOC_DAIFMT_IB_NF:
                /* Invert bit clock */
-               val = SUN8I_I2S_FMT0_BCLK_POLARITY_INVERTED;
+               val = SUN8I_I2S_FMT0_BCLK_POLARITY_INVERTED |
+                     SUN8I_I2S_FMT0_LRCLK_POLARITY_INVERTED;
                break;
        case SND_SOC_DAIFMT_NB_IF:
                /* Invert frame clock */
-               val = SUN8I_I2S_FMT0_LRCLK_POLARITY_INVERTED;
+               val = 0;
                break;
        case SND_SOC_DAIFMT_NB_NF:
-               val = 0;
+               val = SUN8I_I2S_FMT0_LRCLK_POLARITY_INVERTED;
                break;
        default:
                return -EINVAL;