ARM: dts: renesas: r8a73a4: Add cp clock

Add the Common Peripheral (CP) clock, which is driven by the main
clock / 2 during normal system operation, but may be driven by EXTALR
during early system boot, when SYSCLK_EN is still low.  As the latter is
irrelevant to Linux, just model it as a fixed clock driven from
main_div2_clk.

Switch all users of main_div2_clk that are documented to be clocked by
the CP clock to cp_clk, to better reflect the actual clock topology.

Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Reviewed-by: Niklas Söderlund <niklas.soderlund+renesas@ragnatech.se>
Link: https://lore.kernel.org/r/f9826b0755207a1e16871c17daca109fb11f3868.1705315614.git.geert+renesas@glider.be

diff --git a/arch/arm/boot/dts/renesas/r8a73a4.dtsi b/arch/arm/boot/dts/renesas/r8a73a4.dtsi
index d1f4cbd099efb470fe3be42bd9e54c6acbbd5cf5..c2be1934490b5baf601149f0eb88a62baa10054a 100644 (file)
--- a/arch/arm/boot/dts/renesas/r8a73a4.dtsi
+++ b/arch/arm/boot/dts/renesas/r8a73a4.dtsi
@@ -624,6 +624,13 @@
                        clock-div = <2>;
                        clock-mult = <1>;
                };
+               cp_clk: cp {
+                       compatible = "fixed-factor-clock";
+                       clocks = <&main_div2_clk>;
+                       #clock-cells = <0>;
+                       clock-div = <1>;
+                       clock-mult = <1>;
+               };
                pll0_div2_clk: pll0_div2 {
                        compatible = "fixed-factor-clock";
                        clocks = <&cpg_clocks R8A73A4_CLK_PLL0>;
@@ -689,9 +696,8 @@
                mstp4_clks: mstp4_clks@e6150140 {
                        compatible = "renesas,r8a73a4-mstp-clocks", "renesas,cpg-mstp-clocks";
                        reg = <0 0xe6150140 0 4>, <0 0xe615004c 0 4>;
-                       clocks = <&main_div2_clk>, <&cpg_clocks R8A73A4_CLK_ZS>,
-                                <&main_div2_clk>,
-                                <&cpg_clocks R8A73A4_CLK_HP>,
+                       clocks = <&cp_clk>, <&cpg_clocks R8A73A4_CLK_ZS>,
+                                <&cp_clk>, <&cpg_clocks R8A73A4_CLK_HP>,
                                 <&cpg_clocks R8A73A4_CLK_HP>;
                        #clock-cells = <1>;
                        clock-indices = <