drm/xe/xe2: synchronise CS_CHICKEN1 with WMTP support

Recommendation is to read FUSE4 register to check if WMTP has been
enabled/disabled by HW. If enabled we don't need to do anything special,
however if disabled recommendation is to also disable the WMTP mode in
the FF_SLICE_CS_CHICKEN2 register, falling back to thread-group and
mid-batch preemption only. However on Linux, the per-context CS_CHICKEN1
is how userspace controls pre-emption, so instead use the default lrc to
disable WMTP using CS_CHICKEN1, if disabled by HW. Userspace is still
free to set CS_CHICKEN1 to whatever they want later.

v2: remove redundant version check and also add descriptive name(Matt)
v3: remove usage of REG_FIELD_GET(Matt)

Cc: Matt Roper <matthew.d.roper@intel.com>
Co-developed-by: Matthew Auld <matthew.auld@intel.com>
Signed-off-by: Matthew Auld <matthew.auld@intel.com>
Signed-off-by: Nirmoy Das <nirmoy.das@intel.com>
Reviewed-by: Matt Roper <matthew.d.roper@intel.com>
Link: https://lore.kernel.org/r/20240104182615.21327-1-nirmoy.das@intel.com
Signed-off-by: Matt Roper <matthew.d.roper@intel.com>

diff --git a/drivers/gpu/drm/xe/regs/xe_gt_regs.h b/drivers/gpu/drm/xe/regs/xe_gt_regs.h
index 6aaaf1f63c728abf083bdb81af03f802321c3190..6dfad86aaea647151c5f58f622bbce715ac327de 100644 (file)
--- a/drivers/gpu/drm/xe/regs/xe_gt_regs.h
+++ b/drivers/gpu/drm/xe/regs/xe_gt_regs.h
@@ -146,6 +146,7 @@
 
 /* Fuse readout registers for GT */
 #define XEHP_FUSE4                             XE_REG(0x9114)
+#define   CFEG_WMTP_DISABLE                    REG_BIT(20)
 #define   CCS_EN_MASK                          REG_GENMASK(19, 16)
 #define   GT_L3_EXC_MASK                       REG_GENMASK(6, 4)
 

diff --git a/drivers/gpu/drm/xe/xe_hw_engine.c b/drivers/gpu/drm/xe/xe_hw_engine.c
index 832989c83a253408069c4e6ef3bb107aca167cb1..e279ef6c527cd7fbc30015d54231091936b0fbc3 100644 (file)
--- a/drivers/gpu/drm/xe/xe_hw_engine.c
+++ b/drivers/gpu/drm/xe/xe_hw_engine.c
@@ -316,6 +316,19 @@ static bool xe_hw_engine_match_fixed_cslice_mode(const struct xe_gt *gt,
               xe_rtp_match_first_render_or_compute(gt, hwe);
 }
 
+static bool xe_rtp_cfeg_wmtp_disabled(const struct xe_gt *gt,
+                                     const struct xe_hw_engine *hwe)
+{
+       if (GRAPHICS_VER(gt_to_xe(gt)) < 20)
+               return false;
+
+       if (hwe->class != XE_ENGINE_CLASS_COMPUTE &&
+           hwe->class != XE_ENGINE_CLASS_RENDER)
+               return false;
+
+       return xe_mmio_read32(hwe->gt, XEHP_FUSE4) & CFEG_WMTP_DISABLE;
+}
+
 void
 xe_hw_engine_setup_default_lrc_state(struct xe_hw_engine *hwe)
 {
@@ -346,6 +359,14 @@ xe_hw_engine_setup_default_lrc_state(struct xe_hw_engine *hwe)
                  XE_RTP_ACTIONS(FIELD_SET(RCU_MODE, RCU_MODE_FIXED_SLICE_CCS_MODE,
                                           RCU_MODE_FIXED_SLICE_CCS_MODE))
                },
+               /* Disable WMTP if HW doesn't support it */
+               { XE_RTP_NAME("DISABLE_WMTP_ON_UNSUPPORTED_HW"),
+                 XE_RTP_RULES(FUNC(xe_rtp_cfeg_wmtp_disabled)),
+                 XE_RTP_ACTIONS(FIELD_SET(CS_CHICKEN1(0),
+                                          PREEMPT_GPGPU_LEVEL_MASK,
+                                          PREEMPT_GPGPU_THREAD_GROUP_LEVEL)),
+                 XE_RTP_ENTRY_FLAG(FOREACH_ENGINE)
+               },
                {}
        };