arm64: dts: hisilicon: hi3670: Add UFS controller support

Add UFS controller support for HiSilicon HI3670 SoC.

Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
Signed-off-by: Wei Xu <xuwei5@hisilicon.com>

diff --git a/arch/arm64/boot/dts/hisilicon/hi3670.dtsi b/arch/arm64/boot/dts/hisilicon/hi3670.dtsi
index 30177543cc8fce9fd428dbce90c54b4f205f9301..2dcffa3ed2189eb5538ebf72c37ac4924f5d3629 100644 (file)
--- a/arch/arm64/boot/dts/hisilicon/hi3670.dtsi
+++ b/arch/arm64/boot/dts/hisilicon/hi3670.dtsi
@@ -655,6 +655,24 @@
                        clock-names = "apb_pclk";
                };
 
+               /* UFS */
+               ufs: ufs@ff3c0000 {
+                       compatible = "hisilicon,hi3670-ufs", "jedec,ufs-2.1";
+                       /* 0: HCI standard */
+                       /* 1: UFS SYS CTRL */
+                       reg = <0x0 0xff3c0000 0x0 0x1000>,
+                               <0x0 0xff3e0000 0x0 0x1000>;
+                       interrupt-parent = <&gic>;
+                       interrupts = <GIC_SPI 278 IRQ_TYPE_LEVEL_HIGH>;
+                       clocks = <&crg_ctrl HI3670_CLK_GATE_UFSIO_REF>,
+                               <&crg_ctrl HI3670_CLK_GATE_UFS_SUBSYS>;
+                       clock-names = "ref_clk", "phy_clk";
+                       freq-table-hz = <0 0>, <0 0>;
+                       /* offset: 0x84; bit: 12 */
+                       resets = <&crg_rst 0x84 12>;
+                       reset-names = "rst";
+               };
+
                /* SD */
                dwmmc1: dwmmc1@ff37f000 {
                        compatible = "hisilicon,hi3670-dw-mshc",