clk: imx: clk-imx8qxp: Add SCU clocks support for DC0 bypass clocks

This patch adds SCU clocks support for i.MX8qxp DC0 subsystem bypass clocks.

Cc: Michael Turquette <mturquette@baylibre.com>
Cc: Stephen Boyd <sboyd@kernel.org>
Cc: Shawn Guo <shawnguo@kernel.org>
Cc: Sascha Hauer <s.hauer@pengutronix.de>
Cc: Pengutronix Kernel Team <kernel@pengutronix.de>
Cc: Fabio Estevam <festevam@gmail.com>
Cc: NXP Linux Team <linux-imx@nxp.com>
Cc: Dong Aisheng <aisheng.dong@nxp.com>
Cc: Rob Herring <robh+dt@kernel.org>
Signed-off-by: Liu Ying <victor.liu@nxp.com>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>

diff --git a/drivers/clk/imx/clk-imx8qxp.c b/drivers/clk/imx/clk-imx8qxp.c
index b48643e42e8a62b3bf3494416d1742abd5f7e174..af6a5454ad49fb82c3f4b6b7469c88dd40152df6 100644 (file)
--- a/drivers/clk/imx/clk-imx8qxp.c
+++ b/drivers/clk/imx/clk-imx8qxp.c
@@ -119,6 +119,8 @@ static int imx8qxp_clk_probe(struct platform_device *pdev)
        clks[IMX_DC0_DISP1_CLK]         = imx_clk_scu("dc0_disp1_clk", IMX_SC_R_DC_0, IMX_SC_PM_CLK_MISC1, clk_cells);
        clks[IMX_DC0_PLL0_CLK]          = imx_clk_scu("dc0_pll0_clk", IMX_SC_R_DC_0_PLL_0, IMX_SC_PM_CLK_PLL, clk_cells);
        clks[IMX_DC0_PLL1_CLK]          = imx_clk_scu("dc0_pll1_clk", IMX_SC_R_DC_0_PLL_1, IMX_SC_PM_CLK_PLL, clk_cells);
+       clks[IMX_DC0_BYPASS0_CLK]       = imx_clk_scu("dc0_bypass0_clk", IMX_SC_R_DC_0_VIDEO0, IMX_SC_PM_CLK_BYPASS, clk_cells);
+       clks[IMX_DC0_BYPASS1_CLK]       = imx_clk_scu("dc0_bypass1_clk", IMX_SC_R_DC_0_VIDEO1, IMX_SC_PM_CLK_BYPASS, clk_cells);
 
        /* MIPI-LVDS SS */
        clks[IMX_MIPI0_I2C0_CLK]        = imx_clk_scu("mipi0_i2c0_clk", IMX_SC_R_MIPI_0_I2C_0, IMX_SC_PM_CLK_MISC2, clk_cells);

diff --git a/include/dt-bindings/clock/imx8-clock.h b/include/dt-bindings/clock/imx8-clock.h
index 673a8c6623400e4b44c34f0526c5d39e99e5d6c2..82b1fc8d1ee0f987ef2f01a023bccb9fe497ea0e 100644 (file)
--- a/include/dt-bindings/clock/imx8-clock.h
+++ b/include/dt-bindings/clock/imx8-clock.h
@@ -64,6 +64,8 @@
 #define IMX_DC0_PLL1_CLK                               81
 #define IMX_DC0_DISP0_CLK                              82
 #define IMX_DC0_DISP1_CLK                              83
+#define IMX_DC0_BYPASS0_CLK                            84
+#define IMX_DC0_BYPASS1_CLK                            85
 
 /* MIPI-LVDS SS */
 #define IMX_MIPI_IPG_CLK                               90