drm/amdgpu: use the whole doorbell space for mes

Use the whole doorbell space for mes. Each queue in one process occupies
one doorbell slot to ring the queue submitting.

Signed-off-by: Jack Xiao <Jack.Xiao@amd.com>
Acked-by: Christian König <christian.koenig@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
index 53d938d5a00a06b6ce90e3526d4c0c1d48b27b39..9b5d1979ac0e32020bd9c90c8ff156b2e8164710 100644 (file)
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
@@ -1044,19 +1044,25 @@ static int amdgpu_device_doorbell_init(struct amdgpu_device *adev)
        adev->doorbell.base = pci_resource_start(adev->pdev, 2);
        adev->doorbell.size = pci_resource_len(adev->pdev, 2);
 
-       adev->doorbell.num_doorbells = min_t(u32, adev->doorbell.size / sizeof(u32),
-                                            adev->doorbell_index.max_assignment+1);
-       if (adev->doorbell.num_doorbells == 0)
-               return -EINVAL;
-
-       /* For Vega, reserve and map two pages on doorbell BAR since SDMA
-        * paging queue doorbell use the second page. The
-        * AMDGPU_DOORBELL64_MAX_ASSIGNMENT definition assumes all the
-        * doorbells are in the first page. So with paging queue enabled,
-        * the max num_doorbells should + 1 page (0x400 in dword)
-        */
-       if (adev->asic_type >= CHIP_VEGA10)
-               adev->doorbell.num_doorbells += 0x400;
+       if (adev->enable_mes) {
+               adev->doorbell.num_doorbells =
+                       adev->doorbell.size / sizeof(u32);
+       } else {
+               adev->doorbell.num_doorbells =
+                       min_t(u32, adev->doorbell.size / sizeof(u32),
+                             adev->doorbell_index.max_assignment+1);
+               if (adev->doorbell.num_doorbells == 0)
+                       return -EINVAL;
+
+               /* For Vega, reserve and map two pages on doorbell BAR since SDMA
+                * paging queue doorbell use the second page. The
+                * AMDGPU_DOORBELL64_MAX_ASSIGNMENT definition assumes all the
+                * doorbells are in the first page. So with paging queue enabled,
+                * the max num_doorbells should + 1 page (0x400 in dword)
+                */
+               if (adev->asic_type >= CHIP_VEGA10)
+                       adev->doorbell.num_doorbells += 0x400;
+       }
 
        adev->doorbell.ptr = ioremap(adev->doorbell.base,
                                     adev->doorbell.num_doorbells *