mips: dts: ralink: mt7621: reorder pci?_phy attributes

Reorder the attributes of the PCIe PHY nodes node to match
what the DTS style guide recommends.

Signed-off-by: Justin Swartz <justin.swartz@risingedge.co.za>
Reviewed-by: Arınç ÜNAL <arinc.unal@arinc9.com>
Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
Reviewed-by: Sergio Paracuellos <sergio.paracuellos@gmail.com>
Signed-off-by: Thomas Bogendoerfer <tsbogend@alpha.franken.de>

diff --git a/arch/mips/boot/dts/ralink/mt7621.dtsi b/arch/mips/boot/dts/ralink/mt7621.dtsi
index aa06d12acacce85db1502f159894a851d7f26c9e..284811f32929a7d3ce44bbd2396bdd857159a9a1 100644 (file)
--- a/arch/mips/boot/dts/ralink/mt7621.dtsi
+++ b/arch/mips/boot/dts/ralink/mt7621.dtsi
@@ -583,14 +583,18 @@
        pcie0_phy: pcie-phy@1e149000 {
                compatible = "mediatek,mt7621-pci-phy";
                reg = <0x1e149000 0x0700>;
-               clocks = <&sysc MT7621_CLK_XTAL>;
+
                #phy-cells = <1>;
+
+               clocks = <&sysc MT7621_CLK_XTAL>;
        };
 
        pcie2_phy: pcie-phy@1e14a000 {
                compatible = "mediatek,mt7621-pci-phy";
                reg = <0x1e14a000 0x0700>;
-               clocks = <&sysc MT7621_CLK_XTAL>;
+
                #phy-cells = <1>;
+
+               clocks = <&sysc MT7621_CLK_XTAL>;
        };
 };