irqchip/stm32-exti: Mark events reserved with RIF configuration check

EXTI events availability depends on Resource Isolation Framework (RIF)
configuration.

RIF grants access to buses with Compartment ID (CID) filtering, secure and
privilege level. It also assigns EXTI events to one or several processors
(CID, Secure, Privilege).

EXTI events used by Linux must be CID-filtered (EnCIDCFGR.CFEN=1) and
statically assigned to CID1 (EnCIDCFR.CID=CID1).

EXTI events not filling these conditions are marked as reserved and can't
be used by Linux.

Signed-off-by: Antonio Borneo <antonio.borneo@foss.st.com>
Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
Link: https://lore.kernel.org/r/20240415134926.1254428-7-antonio.borneo@foss.st.com

diff --git a/drivers/irqchip/irq-stm32-exti.c b/drivers/irqchip/irq-stm32-exti.c
index c0a020aab557a7bbcc5031da475682cfac51ab6e..2cc9f3b7d6690cc06368b84dbe5a8a40904c9449 100644 (file)
--- a/drivers/irqchip/irq-stm32-exti.c
+++ b/drivers/irqchip/irq-stm32-exti.c
@@ -23,9 +23,22 @@
 
 #include <dt-bindings/interrupt-controller/arm-gic.h>
 
-#define IRQS_PER_BANK 32
+#define IRQS_PER_BANK                  32
 
-#define HWSPNLCK_TIMEOUT       1000 /* usec */
+#define HWSPNLCK_TIMEOUT               1000 /* usec */
+
+#define EXTI_EnCIDCFGR(n)              (0x180 + (n) * 4)
+#define EXTI_HWCFGR1                   0x3f0
+
+/* Register: EXTI_EnCIDCFGR(n) */
+#define EXTI_CIDCFGR_CFEN_MASK         BIT(0)
+#define EXTI_CIDCFGR_CID_MASK          GENMASK(6, 4)
+#define EXTI_CIDCFGR_CID_SHIFT         4
+
+/* Register: EXTI_HWCFGR1 */
+#define EXTI_HWCFGR1_CIDWIDTH_MASK     GENMASK(27, 24)
+
+#define EXTI_CID1                      1
 
 struct stm32_exti_bank {
        u32 imr_ofst;
@@ -907,6 +920,27 @@ static const struct irq_domain_ops stm32_exti_h_domain_ops = {
        .xlate = irq_domain_xlate_twocell,
 };
 
+static void stm32_exti_check_rif(struct stm32_exti_host_data *host_data)
+{
+       unsigned int bank, i, event;
+       u32 cid, cidcfgr, hwcfgr1;
+
+       /* quit on CID not supported */
+       hwcfgr1 = readl_relaxed(host_data->base + EXTI_HWCFGR1);
+       if ((hwcfgr1 & EXTI_HWCFGR1_CIDWIDTH_MASK) == 0)
+               return;
+
+       for (bank = 0; bank < host_data->drv_data->bank_nr; bank++) {
+               for (i = 0; i < IRQS_PER_BANK; i++) {
+                       event = bank * IRQS_PER_BANK + i;
+                       cidcfgr = readl_relaxed(host_data->base + EXTI_EnCIDCFGR(event));
+                       cid = (cidcfgr & EXTI_CIDCFGR_CID_MASK) >> EXTI_CIDCFGR_CID_SHIFT;
+                       if ((cidcfgr & EXTI_CIDCFGR_CFEN_MASK) && cid != EXTI_CID1)
+                               host_data->chips_data[bank].event_reserved |= BIT(i);
+               }
+       }
+}
+
 static void stm32_exti_remove_irq(void *data)
 {
        struct irq_domain *domain = data;
@@ -969,6 +1003,8 @@ static int stm32_exti_probe(struct platform_device *pdev)
        for (i = 0; i < drv_data->bank_nr; i++)
                stm32_exti_chip_init(host_data, i, np);
 
+       stm32_exti_check_rif(host_data);
+
        parent_domain = irq_find_host(of_irq_find_parent(np));
        if (!parent_domain) {
                dev_err(dev, "GIC interrupt-parent not found\n");