chip->cmd_ctrl(mtd, readcmd, ctrl);
                ctrl &= ~NAND_CTRL_CHANGE;
        }
-       chip->cmd_ctrl(mtd, command, ctrl);
+       if (command != NAND_CMD_NONE)
+               chip->cmd_ctrl(mtd, command, ctrl);
 
        /* Address cycle, when necessary */
        ctrl = NAND_CTRL_ALE | NAND_CTRL_CHANGE;
         */
        switch (command) {
 
+       case NAND_CMD_NONE:
        case NAND_CMD_PAGEPROG:
        case NAND_CMD_ERASE1:
        case NAND_CMD_ERASE2:
        }
 
        /* Command latch cycle */
-       chip->cmd_ctrl(mtd, command, NAND_NCE | NAND_CLE | NAND_CTRL_CHANGE);
+       if (command != NAND_CMD_NONE)
+               chip->cmd_ctrl(mtd, command,
+                              NAND_NCE | NAND_CLE | NAND_CTRL_CHANGE);
 
        if (column != -1 || page_addr != -1) {
                int ctrl = NAND_CTRL_CHANGE | NAND_NCE | NAND_ALE;
         */
        switch (command) {
 
+       case NAND_CMD_NONE:
        case NAND_CMD_CACHEDPROG:
        case NAND_CMD_PAGEPROG:
        case NAND_CMD_ERASE1: