drm/amd/display: Only clear symclk otg flag for HDMI

[Description]
There is a corner case where the symclk otg flag is cleared
when disabling the phantom pipe for subvp (because the phantom
and main pipe share the same link). This is undesired because
we need the maintain the correct symclk otg flag state for
the main pipe.

For now only clear the flag only for HDMI signal type, since
it's only set for HDMI signal type (phantom is virtual). The
ideal solution is to not clear it if the stream is phantom but
currently there's a bug that doesn't allow us to do this. Once
this issue is fixed the proper fix can be implemented.

Reviewed-by: Samson Tam <samson.tam@amd.com>
Acked-by: Wayne Lin <wayne.lin@amd.com>
Signed-off-by: Alvin Lee <alvin.lee2@amd.com>
Tested-by: Daniel Wheeler <daniel.wheeler@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

diff --git a/drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c b/drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c
index 762e674f9998c2dc4d819740f5f072696f64cdd9..6457099ed588203f58d47ad72b8ed648ceae2098 100644 (file)
--- a/drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c
+++ b/drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c
@@ -2125,7 +2125,8 @@ static void dce110_reset_hw_ctx_wrap(
                                BREAK_TO_DEBUGGER();
                        }
                        pipe_ctx_old->stream_res.tg->funcs->disable_crtc(pipe_ctx_old->stream_res.tg);
-                       pipe_ctx_old->stream->link->phy_state.symclk_ref_cnts.otg = 0;
+                       if (dc_is_hdmi_tmds_signal(pipe_ctx_old->stream->signal))
+                               pipe_ctx_old->stream->link->phy_state.symclk_ref_cnts.otg = 0;
                        pipe_ctx_old->plane_res.mi->funcs->free_mem_input(
                                        pipe_ctx_old->plane_res.mi, dc->current_state->stream_count);
 

diff --git a/drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c b/drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c
index 632aa091b6b6b2551ba6b2a8f7c103c3d29f0658..1c5e3bb6f0ee418f48fab772f73180e046e59d9d 100644 (file)
--- a/drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c
+++ b/drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c
@@ -1058,7 +1058,8 @@ static void dcn10_reset_back_end_for_pipe(
                if (pipe_ctx->stream_res.tg->funcs->set_drr)
                        pipe_ctx->stream_res.tg->funcs->set_drr(
                                        pipe_ctx->stream_res.tg, NULL);
-               pipe_ctx->stream->link->phy_state.symclk_ref_cnts.otg = 0;
+               if (dc_is_hdmi_tmds_signal(pipe_ctx->stream->signal))
+                       pipe_ctx->stream->link->phy_state.symclk_ref_cnts.otg = 0;
        }
 
        for (i = 0; i < dc->res_pool->pipe_count; i++)

diff --git a/drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c b/drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c
index 88fe102f8288226aa9d9ad9d50a12cdf32bb4cd0..0dfcb3cdcd20c2bfd794438e0e8b484e9dad50a0 100644 (file)
--- a/drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c
+++ b/drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c
@@ -2624,7 +2624,8 @@ static void dcn20_reset_back_end_for_pipe(
                 * the case where the same symclk is shared across multiple otg
                 * instances
                 */
-               link->phy_state.symclk_ref_cnts.otg = 0;
+               if (dc_is_hdmi_tmds_signal(pipe_ctx->stream->signal))
+                       link->phy_state.symclk_ref_cnts.otg = 0;
                if (link->phy_state.symclk_state == SYMCLK_ON_TX_OFF) {
                        link_hwss->disable_link_output(link,
                                        &pipe_ctx->link_res, pipe_ctx->stream->signal);

diff --git a/drivers/gpu/drm/amd/display/dc/hwss/dcn31/dcn31_hwseq.c b/drivers/gpu/drm/amd/display/dc/hwss/dcn31/dcn31_hwseq.c
index 994250b6f2ef8a8b64cfcd62a9e90edba63dabff..260860c259f3a366533142b7faef1325317438dc 100644 (file)
--- a/drivers/gpu/drm/amd/display/dc/hwss/dcn31/dcn31_hwseq.c
+++ b/drivers/gpu/drm/amd/display/dc/hwss/dcn31/dcn31_hwseq.c
@@ -524,7 +524,8 @@ static void dcn31_reset_back_end_for_pipe(
        if (pipe_ctx->stream_res.tg->funcs->set_odm_bypass)
                pipe_ctx->stream_res.tg->funcs->set_odm_bypass(
                                pipe_ctx->stream_res.tg, &pipe_ctx->stream->timing);
-       pipe_ctx->stream->link->phy_state.symclk_ref_cnts.otg = 0;
+       if (dc_is_hdmi_tmds_signal(pipe_ctx->stream->signal))
+               pipe_ctx->stream->link->phy_state.symclk_ref_cnts.otg = 0;
 
        if (pipe_ctx->stream_res.tg->funcs->set_drr)
                pipe_ctx->stream_res.tg->funcs->set_drr(