drm/msm/dpu: Fix VBIF_XINL_QOS_LVL_REMAP_000 register offset

On DPUs prior to version 4 the VBIF_XINL_QOS_LVL_REMAP_000 register
is at 0x570 offset from vbif base instead of 0x590, due to the
VBIF_XINL_QOS_RP_REMAP_000 having less instances (less possible XINs).

Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@somainline.org>
Signed-off-by: Rob Clark <robdclark@chromium.org>

diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_vbif.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_vbif.c
index cf867f3f7c36f0e8fc261a9bf99cb84a63f3b4a4..b757054e1c23fa72093ddeab12ab22c705dcfe05 100644 (file)
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_vbif.c
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_vbif.c
@@ -30,7 +30,7 @@
 #define VBIF_XIN_HALT_CTRL0            0x0200
 #define VBIF_XIN_HALT_CTRL1            0x0204
 #define VBIF_XINL_QOS_RP_REMAP_000     0x0550
-#define VBIF_XINL_QOS_LVL_REMAP_000    0x0590
+#define VBIF_XINL_QOS_LVL_REMAP_000(v) (v < DPU_HW_VER_400 ? 0x570 : 0x0590)
 
 static void dpu_hw_clear_errors(struct dpu_hw_vbif *vbif,
                u32 *pnd_errors, u32 *src_errors)
@@ -156,18 +156,19 @@ static void dpu_hw_set_qos_remap(struct dpu_hw_vbif *vbif,
                u32 xin_id, u32 level, u32 remap_level)
 {
        struct dpu_hw_blk_reg_map *c;
-       u32 reg_val, reg_val_lvl, mask, reg_high, reg_shift;
+       u32 reg_lvl, reg_val, reg_val_lvl, mask, reg_high, reg_shift;
 
        if (!vbif)
                return;
 
        c = &vbif->hw;
 
+       reg_lvl = VBIF_XINL_QOS_LVL_REMAP_000(c->hwversion);
        reg_high = ((xin_id & 0x8) >> 3) * 4 + (level * 8);
        reg_shift = (xin_id & 0x7) * 4;
 
        reg_val = DPU_REG_READ(c, VBIF_XINL_QOS_RP_REMAP_000 + reg_high);
-       reg_val_lvl = DPU_REG_READ(c, VBIF_XINL_QOS_LVL_REMAP_000 + reg_high);
+       reg_val_lvl = DPU_REG_READ(c, reg_lvl + reg_high);
 
        mask = 0x7 << reg_shift;
 
@@ -178,7 +179,7 @@ static void dpu_hw_set_qos_remap(struct dpu_hw_vbif *vbif,
        reg_val_lvl |= (remap_level << reg_shift) & mask;
 
        DPU_REG_WRITE(c, VBIF_XINL_QOS_RP_REMAP_000 + reg_high, reg_val);
-       DPU_REG_WRITE(c, VBIF_XINL_QOS_LVL_REMAP_000 + reg_high, reg_val_lvl);
+       DPU_REG_WRITE(c, reg_lvl + reg_high, reg_val_lvl);
 }
 
 static void dpu_hw_set_write_gather_en(struct dpu_hw_vbif *vbif, u32 xin_id)