mtd: rawnand: Rename the ECC algorithm enumeration items

NAND_ECC_ is not a meaningful prefix, use NAND_ECC_ALGO_ instead.

Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com>
Reviewed-by: Boris Brezillon <boris.brezillon@collabora.com>
Link: https://lore.kernel.org/linux-mtd/20200827085208.16276-3-miquel.raynal@bootlin.com

diff --git a/drivers/mtd/nand/raw/ams-delta.c b/drivers/mtd/nand/raw/ams-delta.c
index fdba155416d25bdb83e617b04ac2fd6a905cb1f0..21199d9ae9be21232bb55e46b35458f2a00a40e8 100644 (file)
--- a/drivers/mtd/nand/raw/ams-delta.c
+++ b/drivers/mtd/nand/raw/ams-delta.c
@@ -261,7 +261,7 @@ static int gpio_nand_probe(struct platform_device *pdev)
        }
 
        this->ecc.mode = NAND_ECC_SOFT;
-       this->ecc.algo = NAND_ECC_HAMMING;
+       this->ecc.algo = NAND_ECC_ALGO_HAMMING;
 
        platform_set_drvdata(pdev, priv);
 

diff --git a/drivers/mtd/nand/raw/arasan-nand-controller.c b/drivers/mtd/nand/raw/arasan-nand-controller.c
index 12c643e97c852598e039a1bcf1648df418f2fc73..b0616a95340defcde2d2c2756f11e4cf9ca36d5f 100644 (file)
--- a/drivers/mtd/nand/raw/arasan-nand-controller.c
+++ b/drivers/mtd/nand/raw/arasan-nand-controller.c
@@ -983,7 +983,7 @@ static int anfc_init_hw_ecc_controller(struct arasan_nfc *nfc,
        mtd_set_ooblayout(mtd, &nand_ooblayout_lp_ops);
 
        ecc->steps = mtd->writesize / ecc->size;
-       ecc->algo = NAND_ECC_BCH;
+       ecc->algo = NAND_ECC_ALGO_BCH;
        anand->ecc_bits = bch_gf_mag * ecc->strength;
        ecc->bytes = DIV_ROUND_UP(anand->ecc_bits, 8);
        anand->ecc_total = DIV_ROUND_UP(anand->ecc_bits * ecc->steps, 8);

diff --git a/drivers/mtd/nand/raw/atmel/nand-controller.c b/drivers/mtd/nand/raw/atmel/nand-controller.c
index c9818f548d079726a09c58c29b54dac5ae4f5276..8999571bfa5ddbad60dd3f2c19a8102f569391cc 100644 (file)
--- a/drivers/mtd/nand/raw/atmel/nand-controller.c
+++ b/drivers/mtd/nand/raw/atmel/nand-controller.c
@@ -1099,7 +1099,7 @@ static int atmel_nand_pmecc_init(struct nand_chip *chip)
        if (IS_ERR(nand->pmecc))
                return PTR_ERR(nand->pmecc);
 
-       chip->ecc.algo = NAND_ECC_BCH;
+       chip->ecc.algo = NAND_ECC_ALGO_BCH;
        chip->ecc.size = req.ecc.sectorsize;
        chip->ecc.bytes = req.ecc.bytes / req.ecc.nsectors;
        chip->ecc.strength = req.ecc.strength;

diff --git a/drivers/mtd/nand/raw/au1550nd.c b/drivers/mtd/nand/raw/au1550nd.c
index d865200ccd08f6cb39827a435749396ea6e86b8f..ec2d90ad87dee5e857dda42fff11e0570fbcb8c1 100644 (file)
--- a/drivers/mtd/nand/raw/au1550nd.c
+++ b/drivers/mtd/nand/raw/au1550nd.c
@@ -295,7 +295,7 @@ static int au1550nd_probe(struct platform_device *pdev)
        ctx->controller.ops = &au1550nd_ops;
        this->controller = &ctx->controller;
        this->ecc.mode = NAND_ECC_SOFT;
-       this->ecc.algo = NAND_ECC_HAMMING;
+       this->ecc.algo = NAND_ECC_ALGO_HAMMING;
 
        if (pd->devwidth)
                this->options |= NAND_BUSWIDTH_16;

diff --git a/drivers/mtd/nand/raw/brcmnand/brcmnand.c b/drivers/mtd/nand/raw/brcmnand/brcmnand.c
index a4033d32a71033c9dfe12ea9c089c67f441ecbec..39f1bf327592501fd3449764c43acaedcbd8728b 100644 (file)
--- a/drivers/mtd/nand/raw/brcmnand/brcmnand.c
+++ b/drivers/mtd/nand/raw/brcmnand/brcmnand.c
@@ -2571,17 +2571,17 @@ static int brcmnand_setup_dev(struct brcmnand_host *host)
                return -EINVAL;
        }
 
-       if (chip->ecc.algo == NAND_ECC_UNKNOWN) {
+       if (chip->ecc.algo == NAND_ECC_ALGO_UNKNOWN) {
                if (chip->ecc.strength == 1 && chip->ecc.size == 512)
                        /* Default to Hamming for 1-bit ECC, if unspecified */
-                       chip->ecc.algo = NAND_ECC_HAMMING;
+                       chip->ecc.algo = NAND_ECC_ALGO_HAMMING;
                else
                        /* Otherwise, BCH */
-                       chip->ecc.algo = NAND_ECC_BCH;
+                       chip->ecc.algo = NAND_ECC_ALGO_BCH;
        }
 
-       if (chip->ecc.algo == NAND_ECC_HAMMING && (chip->ecc.strength != 1 ||
-                                                  chip->ecc.size != 512)) {
+       if (chip->ecc.algo == NAND_ECC_ALGO_HAMMING &&
+           (chip->ecc.strength != 1 || chip->ecc.size != 512)) {
                dev_err(ctrl->dev, "invalid Hamming params: %d bits per %d bytes\n",
                        chip->ecc.strength, chip->ecc.size);
                return -EINVAL;
@@ -2600,7 +2600,7 @@ static int brcmnand_setup_dev(struct brcmnand_host *host)
 
        switch (chip->ecc.size) {
        case 512:
-               if (chip->ecc.algo == NAND_ECC_HAMMING)
+               if (chip->ecc.algo == NAND_ECC_ALGO_HAMMING)
                        cfg->ecc_level = 15;
                else
                        cfg->ecc_level = chip->ecc.strength;

diff --git a/drivers/mtd/nand/raw/davinci_nand.c b/drivers/mtd/nand/raw/davinci_nand.c
index d975a62caaa5d8bcb42cd78bf27af6a4662188d5..551515c223bb652159184a0d339a8cc8c00218cb 100644 (file)
--- a/drivers/mtd/nand/raw/davinci_nand.c
+++ b/drivers/mtd/nand/raw/davinci_nand.c
@@ -593,11 +593,11 @@ static int davinci_nand_attach_chip(struct nand_chip *chip)
                pdata->ecc_bits = 0;
                /*
                 * This driver expects Hamming based ECC when ecc_mode is set
-                * to NAND_ECC_SOFT. Force ecc.algo to NAND_ECC_HAMMING to
+                * to NAND_ECC_SOFT. Force ecc.algo to NAND_ECC_ALGO_HAMMING to
                 * avoid adding an extra ->ecc_algo field to
                 * davinci_nand_pdata.
                 */
-               info->chip.ecc.algo = NAND_ECC_HAMMING;
+               info->chip.ecc.algo = NAND_ECC_ALGO_HAMMING;
                break;
        case NAND_ECC_HW:
                if (pdata->ecc_bits == 4) {
@@ -629,7 +629,7 @@ static int davinci_nand_attach_chip(struct nand_chip *chip)
                        info->chip.ecc.hwctl = nand_davinci_hwctl_4bit;
                        info->chip.ecc.bytes = 10;
                        info->chip.ecc.options = NAND_ECC_GENERIC_ERASED_CHECK;
-                       info->chip.ecc.algo = NAND_ECC_BCH;
+                       info->chip.ecc.algo = NAND_ECC_ALGO_BCH;
 
                        /*
                         * Update ECC layout if needed ... for 1-bit HW ECC, the
@@ -656,7 +656,7 @@ static int davinci_nand_attach_chip(struct nand_chip *chip)
                        info->chip.ecc.correct = nand_davinci_correct_1bit;
                        info->chip.ecc.hwctl = nand_davinci_hwctl_1bit;
                        info->chip.ecc.bytes = 3;
-                       info->chip.ecc.algo = NAND_ECC_HAMMING;
+                       info->chip.ecc.algo = NAND_ECC_ALGO_HAMMING;
                }
                info->chip.ecc.size = 512;
                info->chip.ecc.strength = pdata->ecc_bits;

diff --git a/drivers/mtd/nand/raw/fsl_elbc_nand.c b/drivers/mtd/nand/raw/fsl_elbc_nand.c
index 088692b2e27a730fcfa25973df7f791f2e462956..da89389faaaeb7e547eaa4069ac5a6925e6e10be 100644 (file)
--- a/drivers/mtd/nand/raw/fsl_elbc_nand.c
+++ b/drivers/mtd/nand/raw/fsl_elbc_nand.c
@@ -748,7 +748,7 @@ static int fsl_elbc_attach_chip(struct nand_chip *chip)
                } else {
                        /* otherwise fall back to default software ECC */
                        chip->ecc.mode = NAND_ECC_SOFT;
-                       chip->ecc.algo = NAND_ECC_HAMMING;
+                       chip->ecc.algo = NAND_ECC_ALGO_HAMMING;
                }
                break;
 

diff --git a/drivers/mtd/nand/raw/fsl_ifc_nand.c b/drivers/mtd/nand/raw/fsl_ifc_nand.c
index 00ae7a910b0328b02d35f95919f7ceb5cb81f9f8..b2ae759dd14e6811c66dbdb1fd37829ff3b53ad7 100644 (file)
--- a/drivers/mtd/nand/raw/fsl_ifc_nand.c
+++ b/drivers/mtd/nand/raw/fsl_ifc_nand.c
@@ -926,7 +926,7 @@ static int fsl_ifc_chip_init(struct fsl_ifc_mtd *priv)
                }
        } else {
                chip->ecc.mode = NAND_ECC_SOFT;
-               chip->ecc.algo = NAND_ECC_HAMMING;
+               chip->ecc.algo = NAND_ECC_ALGO_HAMMING;
        }
 
        ret = fsl_ifc_sram_init(priv);

diff --git a/drivers/mtd/nand/raw/fsl_upm.c b/drivers/mtd/nand/raw/fsl_upm.c
index 197850aeb261198f45407125c3c32398725abb03..04cf7d14082a59a68af1684ff82a43114f741557 100644 (file)
--- a/drivers/mtd/nand/raw/fsl_upm.c
+++ b/drivers/mtd/nand/raw/fsl_upm.c
@@ -48,7 +48,7 @@ static int fun_chip_init(struct fsl_upm_nand *fun,
        struct device_node *flash_np;
 
        fun->chip.ecc.mode = NAND_ECC_SOFT;
-       fun->chip.ecc.algo = NAND_ECC_HAMMING;
+       fun->chip.ecc.algo = NAND_ECC_ALGO_HAMMING;
        fun->chip.controller = &fun->base;
        mtd->dev.parent = fun->dev;
 

diff --git a/drivers/mtd/nand/raw/fsmc_nand.c b/drivers/mtd/nand/raw/fsmc_nand.c
index 92ddc41d0ff002d5fb38df6466f078aa757a69fb..580b9fe8ca4224d6564e7739d612f3170bf7ea0e 100644 (file)
--- a/drivers/mtd/nand/raw/fsmc_nand.c
+++ b/drivers/mtd/nand/raw/fsmc_nand.c
@@ -911,7 +911,7 @@ static int fsmc_nand_attach_chip(struct nand_chip *nand)
                break;
 
        case NAND_ECC_SOFT:
-               if (nand->ecc.algo == NAND_ECC_BCH) {
+               if (nand->ecc.algo == NAND_ECC_ALGO_BCH) {
                        dev_info(host->dev,
                                 "Using 4-bit SW BCH ECC scheme\n");
                        break;

diff --git a/drivers/mtd/nand/raw/gpio.c b/drivers/mtd/nand/raw/gpio.c
index 3bd847ccc3f369ca271efa97296959d96780eace..c8f498eaabeb29bd87bdbac79fa348cedab6eed3 100644 (file)
--- a/drivers/mtd/nand/raw/gpio.c
+++ b/drivers/mtd/nand/raw/gpio.c
@@ -343,7 +343,7 @@ static int gpio_nand_probe(struct platform_device *pdev)
 
        nand_set_flash_node(chip, pdev->dev.of_node);
        chip->ecc.mode          = NAND_ECC_SOFT;
-       chip->ecc.algo          = NAND_ECC_HAMMING;
+       chip->ecc.algo          = NAND_ECC_ALGO_HAMMING;
        chip->options           = gpiomtd->plat.options;
        chip->controller        = &gpiomtd->base;
 

diff --git a/drivers/mtd/nand/raw/marvell_nand.c b/drivers/mtd/nand/raw/marvell_nand.c
index 8482d3bd8b1f5f6fa1ccdc17eb8b88d7ba951830..b2200aa787f29873ebebabd8bfd15c1570ec9c7a 100644 (file)
--- a/drivers/mtd/nand/raw/marvell_nand.c
+++ b/drivers/mtd/nand/raw/marvell_nand.c
@@ -780,7 +780,7 @@ static void marvell_nfc_enable_hw_ecc(struct nand_chip *chip)
                 * When enabling BCH, set threshold to 0 to always know the
                 * number of corrected bitflips.
                 */
-               if (chip->ecc.algo == NAND_ECC_BCH)
+               if (chip->ecc.algo == NAND_ECC_ALGO_BCH)
                        writel_relaxed(NDECCCTRL_BCH_EN, nfc->regs + NDECCCTRL);
        }
 }
@@ -792,7 +792,7 @@ static void marvell_nfc_disable_hw_ecc(struct nand_chip *chip)
 
        if (ndcr & NDCR_ECC_EN) {
                writel_relaxed(ndcr & ~NDCR_ECC_EN, nfc->regs + NDCR);
-               if (chip->ecc.algo == NAND_ECC_BCH)
+               if (chip->ecc.algo == NAND_ECC_ALGO_BCH)
                        writel_relaxed(0, nfc->regs + NDECCCTRL);
        }
 }
@@ -966,7 +966,7 @@ static int marvell_nfc_hw_ecc_check_bitflips(struct nand_chip *chip,
        if (ndsr & NDSR_CORERR) {
                writel_relaxed(ndsr, nfc->regs + NDSR);
 
-               if (chip->ecc.algo == NAND_ECC_BCH)
+               if (chip->ecc.algo == NAND_ECC_ALGO_BCH)
                        bf = NDSR_ERRCNT(ndsr);
                else
                        bf = 1;
@@ -2218,7 +2218,7 @@ static int marvell_nand_hw_ecc_controller_init(struct mtd_info *mtd,
        ecc->size = l->data_bytes;
 
        if (ecc->strength == 1) {
-               chip->ecc.algo = NAND_ECC_HAMMING;
+               chip->ecc.algo = NAND_ECC_ALGO_HAMMING;
                ecc->read_page_raw = marvell_nfc_hw_ecc_hmg_read_page_raw;
                ecc->read_page = marvell_nfc_hw_ecc_hmg_read_page;
                ecc->read_oob_raw = marvell_nfc_hw_ecc_hmg_read_oob_raw;
@@ -2228,7 +2228,7 @@ static int marvell_nand_hw_ecc_controller_init(struct mtd_info *mtd,
                ecc->write_oob_raw = marvell_nfc_hw_ecc_hmg_write_oob_raw;
                ecc->write_oob = ecc->write_oob_raw;
        } else {
-               chip->ecc.algo = NAND_ECC_BCH;
+               chip->ecc.algo = NAND_ECC_ALGO_BCH;
                ecc->strength = 16;
                ecc->read_page_raw = marvell_nfc_hw_ecc_bch_read_page_raw;
                ecc->read_page = marvell_nfc_hw_ecc_bch_read_page;

diff --git a/drivers/mtd/nand/raw/mpc5121_nfc.c b/drivers/mtd/nand/raw/mpc5121_nfc.c
index 18ecb096a32dee82728c9f96965148361c27aa25..a67eded226db6b2ff7c4bc4128d92c73caf375d2 100644 (file)
--- a/drivers/mtd/nand/raw/mpc5121_nfc.c
+++ b/drivers/mtd/nand/raw/mpc5121_nfc.c
@@ -689,7 +689,7 @@ static int mpc5121_nfc_probe(struct platform_device *op)
        chip->legacy.get_features = nand_get_set_features_notsupp;
        chip->bbt_options = NAND_BBT_USE_FLASH;
        chip->ecc.mode = NAND_ECC_SOFT;
-       chip->ecc.algo = NAND_ECC_HAMMING;
+       chip->ecc.algo = NAND_ECC_ALGO_HAMMING;
 
        /* Support external chip-select logic on ADS5121 board */
        if (of_machine_is_compatible("fsl,mpc5121ads")) {

diff --git a/drivers/mtd/nand/raw/mxc_nand.c b/drivers/mtd/nand/raw/mxc_nand.c
index a043d76b48cba59e8300c6dc40f39f2c62b5f413..65448fb223b8d37c3922f3da6fb90aa55aeac761 100644 (file)
--- a/drivers/mtd/nand/raw/mxc_nand.c
+++ b/drivers/mtd/nand/raw/mxc_nand.c
@@ -1846,7 +1846,7 @@ static int mxcnd_probe(struct platform_device *pdev)
                this->ecc.mode = NAND_ECC_HW;
        } else {
                this->ecc.mode = NAND_ECC_SOFT;
-               this->ecc.algo = NAND_ECC_HAMMING;
+               this->ecc.algo = NAND_ECC_ALGO_HAMMING;
        }
 
        /* NAND bus width determines access functions used by upper layer */

diff --git a/drivers/mtd/nand/raw/nand_base.c b/drivers/mtd/nand/raw/nand_base.c
index 0c768cb88f9627a3072d097c5e02e7b8e3107a05..e22a7f9986b12dbfb677b743f58ef375bc8bcab5 100644 (file)
--- a/drivers/mtd/nand/raw/nand_base.c
+++ b/drivers/mtd/nand/raw/nand_base.c
@@ -5066,9 +5066,9 @@ static int of_get_nand_ecc_mode(struct device_node *np)
 }
 
 static const char * const nand_ecc_algos[] = {
-       [NAND_ECC_HAMMING]      = "hamming",
-       [NAND_ECC_BCH]          = "bch",
-       [NAND_ECC_RS]           = "rs",
+       [NAND_ECC_ALGO_HAMMING] = "hamming",
+       [NAND_ECC_ALGO_BCH]     = "bch",
+       [NAND_ECC_ALGO_RS]      = "rs",
 };
 
 static enum nand_ecc_algo of_get_nand_ecc_algo(struct device_node *np)
@@ -5079,7 +5079,7 @@ static enum nand_ecc_algo of_get_nand_ecc_algo(struct device_node *np)
 
        err = of_property_read_string(np, "nand-ecc-algo", &pm);
        if (!err) {
-               for (ecc_algo = NAND_ECC_HAMMING;
+               for (ecc_algo = NAND_ECC_ALGO_HAMMING;
                     ecc_algo < ARRAY_SIZE(nand_ecc_algos);
                     ecc_algo++) {
                        if (!strcasecmp(pm, nand_ecc_algos[ecc_algo]))
@@ -5094,12 +5094,12 @@ static enum nand_ecc_algo of_get_nand_ecc_algo(struct device_node *np)
        err = of_property_read_string(np, "nand-ecc-mode", &pm);
        if (!err) {
                if (!strcasecmp(pm, "soft"))
-                       return NAND_ECC_HAMMING;
+                       return NAND_ECC_ALGO_HAMMING;
                else if (!strcasecmp(pm, "soft_bch"))
-                       return NAND_ECC_BCH;
+                       return NAND_ECC_ALGO_BCH;
        }
 
-       return NAND_ECC_UNKNOWN;
+       return NAND_ECC_ALGO_UNKNOWN;
 }
 
 static int of_get_nand_ecc_step_size(struct device_node *np)
@@ -5167,7 +5167,7 @@ static int nand_dt_init(struct nand_chip *chip)
        if (ecc_mode >= 0)
                chip->ecc.mode = ecc_mode;
 
-       if (ecc_algo != NAND_ECC_UNKNOWN)
+       if (ecc_algo != NAND_ECC_ALGO_UNKNOWN)
                chip->ecc.algo = ecc_algo;
 
        if (ecc_strength >= 0)
@@ -5291,7 +5291,7 @@ static int nand_set_ecc_soft_ops(struct nand_chip *chip)
                return -EINVAL;
 
        switch (ecc->algo) {
-       case NAND_ECC_HAMMING:
+       case NAND_ECC_ALGO_HAMMING:
                ecc->calculate = nand_calculate_ecc;
                ecc->correct = nand_correct_data;
                ecc->read_page = nand_read_page_swecc;
@@ -5312,7 +5312,7 @@ static int nand_set_ecc_soft_ops(struct nand_chip *chip)
                        ecc->options |= NAND_ECC_SOFT_HAMMING_SM_ORDER;
 
                return 0;
-       case NAND_ECC_BCH:
+       case NAND_ECC_ALGO_BCH:
                if (!mtd_nand_has_bch()) {
                        WARN(1, "CONFIG_MTD_NAND_ECC_SW_BCH not enabled\n");
                        return -EINVAL;
@@ -5752,7 +5752,7 @@ static int nand_scan_tail(struct nand_chip *chip)
         * If no default placement scheme is given, select an appropriate one.
         */
        if (!mtd->ooblayout &&
-           !(ecc->mode == NAND_ECC_SOFT && ecc->algo == NAND_ECC_BCH)) {
+           !(ecc->mode == NAND_ECC_SOFT && ecc->algo == NAND_ECC_ALGO_BCH)) {
                switch (mtd->oobsize) {
                case 8:
                case 16:
@@ -5843,7 +5843,7 @@ static int nand_scan_tail(struct nand_chip *chip)
                pr_warn("%d byte HW ECC not possible on %d byte page size, fallback to SW ECC\n",
                        ecc->size, mtd->writesize);
                ecc->mode = NAND_ECC_SOFT;
-               ecc->algo = NAND_ECC_HAMMING;
+               ecc->algo = NAND_ECC_ALGO_HAMMING;
                fallthrough;
        case NAND_ECC_SOFT:
                ret = nand_set_ecc_soft_ops(chip);
@@ -6102,7 +6102,7 @@ EXPORT_SYMBOL(nand_scan_with_ids);
 void nand_cleanup(struct nand_chip *chip)
 {
        if (chip->ecc.mode == NAND_ECC_SOFT &&
-           chip->ecc.algo == NAND_ECC_BCH)
+           chip->ecc.algo == NAND_ECC_ALGO_BCH)
                nand_bch_free((struct nand_bch_control *)chip->ecc.priv);
 
        nanddev_cleanup(&chip->base);

diff --git a/drivers/mtd/nand/raw/nand_micron.c b/drivers/mtd/nand/raw/nand_micron.c
index 4385092a9325b0107e51d047f4beb15223ad144e..2d54a3aa15b1bd22732d4febc7b36428f804c94f 100644 (file)
--- a/drivers/mtd/nand/raw/nand_micron.c
+++ b/drivers/mtd/nand/raw/nand_micron.c
@@ -543,7 +543,7 @@ static int micron_nand_init(struct nand_chip *chip)
                chip->ecc.bytes = chip->base.eccreq.strength * 2;
                chip->ecc.size = 512;
                chip->ecc.strength = chip->base.eccreq.strength;
-               chip->ecc.algo = NAND_ECC_BCH;
+               chip->ecc.algo = NAND_ECC_ALGO_BCH;
                chip->ecc.read_page = micron_nand_read_page_on_die_ecc;
                chip->ecc.write_page = micron_nand_write_page_on_die_ecc;
 

diff --git a/drivers/mtd/nand/raw/nandsim.c b/drivers/mtd/nand/raw/nandsim.c
index f5a53aac3c5ff3fe4cbe287f8f8ef23d7ef0e115..1ab849ccaa96382a24107d823ce95b605676982d 100644 (file)
--- a/drivers/mtd/nand/raw/nandsim.c
+++ b/drivers/mtd/nand/raw/nandsim.c
@@ -2235,7 +2235,7 @@ static int ns_attach_chip(struct nand_chip *chip)
        }
 
        chip->ecc.mode = NAND_ECC_SOFT;
-       chip->ecc.algo = NAND_ECC_BCH;
+       chip->ecc.algo = NAND_ECC_ALGO_BCH;
        chip->ecc.size = 512;
        chip->ecc.strength = bch;
        chip->ecc.bytes = eccbytes;
@@ -2275,7 +2275,7 @@ static int __init ns_init_module(void)
        nand_set_controller_data(chip, (void *)ns);
 
        chip->ecc.mode   = NAND_ECC_SOFT;
-       chip->ecc.algo   = NAND_ECC_HAMMING;
+       chip->ecc.algo   = NAND_ECC_ALGO_HAMMING;
        /* The NAND_SKIP_BBTSCAN option is necessary for 'overridesize' */
        /* and 'badblocks' parameters to work */
        chip->options   |= NAND_SKIP_BBTSCAN;

diff --git a/drivers/mtd/nand/raw/omap2.c b/drivers/mtd/nand/raw/omap2.c
index eb7fcfd9276b7e260a95340eea90fdd165e851a1..967ddbda1c485a9063370832530116c9a9cbe4cd 100644 (file)
--- a/drivers/mtd/nand/raw/omap2.c
+++ b/drivers/mtd/nand/raw/omap2.c
@@ -2011,7 +2011,7 @@ static int omap_nand_attach_chip(struct nand_chip *chip)
         */
        if (info->ecc_opt == OMAP_ECC_HAM1_CODE_SW) {
                chip->ecc.mode = NAND_ECC_SOFT;
-               chip->ecc.algo = NAND_ECC_HAMMING;
+               chip->ecc.algo = NAND_ECC_ALGO_HAMMING;
                return 0;
        }
 

diff --git a/drivers/mtd/nand/raw/orion_nand.c b/drivers/mtd/nand/raw/orion_nand.c
index 880b54ca1b41424d6add40655257fa34ef5f9a71..7a5cfa3d883f78e10a4f9e7ebcce1c6bcbb0e5cd 100644 (file)
--- a/drivers/mtd/nand/raw/orion_nand.c
+++ b/drivers/mtd/nand/raw/orion_nand.c
@@ -140,7 +140,7 @@ static int __init orion_nand_probe(struct platform_device *pdev)
        nc->legacy.cmd_ctrl = orion_nand_cmd_ctrl;
        nc->legacy.read_buf = orion_nand_read_buf;
        nc->ecc.mode = NAND_ECC_SOFT;
-       nc->ecc.algo = NAND_ECC_HAMMING;
+       nc->ecc.algo = NAND_ECC_ALGO_HAMMING;
 
        if (board->chip_delay)
                nc->legacy.chip_delay = board->chip_delay;

diff --git a/drivers/mtd/nand/raw/pasemi_nand.c b/drivers/mtd/nand/raw/pasemi_nand.c
index d8eca8c3fdcd8f471d27af10d3fa01d54ea2aa1d..3eddc284614d4fdfcd03a945bf432a2a87010639 100644 (file)
--- a/drivers/mtd/nand/raw/pasemi_nand.c
+++ b/drivers/mtd/nand/raw/pasemi_nand.c
@@ -133,7 +133,7 @@ static int pasemi_nand_probe(struct platform_device *ofdev)
        chip->legacy.write_buf = pasemi_write_buf;
        chip->legacy.chip_delay = 0;
        chip->ecc.mode = NAND_ECC_SOFT;
-       chip->ecc.algo = NAND_ECC_HAMMING;
+       chip->ecc.algo = NAND_ECC_ALGO_HAMMING;
 
        /* Enable the following for a flash based bad block table */
        chip->bbt_options = NAND_BBT_USE_FLASH;

diff --git a/drivers/mtd/nand/raw/plat_nand.c b/drivers/mtd/nand/raw/plat_nand.c
index 556182f2605776c5247bf7a378014fb0a16b94ad..dbc089c8872faaf45034eba5a85778cc3a5b8a7c 100644 (file)
--- a/drivers/mtd/nand/raw/plat_nand.c
+++ b/drivers/mtd/nand/raw/plat_nand.c
@@ -67,7 +67,7 @@ static int plat_nand_probe(struct platform_device *pdev)
        data->chip.bbt_options |= pdata->chip.bbt_options;
 
        data->chip.ecc.mode = NAND_ECC_SOFT;
-       data->chip.ecc.algo = NAND_ECC_HAMMING;
+       data->chip.ecc.algo = NAND_ECC_ALGO_HAMMING;
 
        platform_set_drvdata(pdev, data);
 

diff --git a/drivers/mtd/nand/raw/s3c2410.c b/drivers/mtd/nand/raw/s3c2410.c
index 10552220597907b20614ad6ae57a4815c91b86e4..5a39002d67eff4503c442fa80a73d3d5e56d9d1e 100644 (file)
--- a/drivers/mtd/nand/raw/s3c2410.c
+++ b/drivers/mtd/nand/raw/s3c2410.c
@@ -938,11 +938,11 @@ static int s3c2410_nand_attach_chip(struct nand_chip *chip)
        case NAND_ECC_SOFT:
                /*
                 * This driver expects Hamming based ECC when ecc_mode is set
-                * to NAND_ECC_SOFT. Force ecc.algo to NAND_ECC_HAMMING to
+                * to NAND_ECC_SOFT. Force ecc.algo to NAND_ECC_ALGO_HAMMING to
                 * avoid adding an extra ecc_algo field to
                 * s3c2410_platform_nand.
                 */
-               chip->ecc.algo = NAND_ECC_HAMMING;
+               chip->ecc.algo = NAND_ECC_ALGO_HAMMING;
                dev_info(info->device, "soft ECC\n");
                break;
 

diff --git a/drivers/mtd/nand/raw/sh_flctl.c b/drivers/mtd/nand/raw/sh_flctl.c
index a661b8bb2dd566ecdcdfbf628bc9c178a263f716..9dbd6fdbe264b9baf22c629017b2f15ad92dee9a 100644 (file)
--- a/drivers/mtd/nand/raw/sh_flctl.c
+++ b/drivers/mtd/nand/raw/sh_flctl.c
@@ -1045,7 +1045,7 @@ static int flctl_chip_attach_chip(struct nand_chip *chip)
                flctl->flcmncr_base |= _4ECCEN;
        } else {
                chip->ecc.mode = NAND_ECC_SOFT;
-               chip->ecc.algo = NAND_ECC_HAMMING;
+               chip->ecc.algo = NAND_ECC_ALGO_HAMMING;
        }
 
        return 0;

diff --git a/drivers/mtd/nand/raw/socrates_nand.c b/drivers/mtd/nand/raw/socrates_nand.c
index 243b34cfbc1b2a0e0a898c60c5a691eddb7ec9cb..72a3a7f98282678f9e87a1c8aab51bd870228cd9 100644 (file)
--- a/drivers/mtd/nand/raw/socrates_nand.c
+++ b/drivers/mtd/nand/raw/socrates_nand.c
@@ -154,7 +154,7 @@ static int socrates_nand_probe(struct platform_device *ofdev)
        nand_chip->legacy.dev_ready = socrates_nand_device_ready;
 
        nand_chip->ecc.mode = NAND_ECC_SOFT;    /* enable ECC */
-       nand_chip->ecc.algo = NAND_ECC_HAMMING;
+       nand_chip->ecc.algo = NAND_ECC_ALGO_HAMMING;
 
        /* TODO: I have no idea what real delay is. */
        nand_chip->legacy.chip_delay = 20;      /* 20us command delay time */

diff --git a/drivers/mtd/nand/raw/tango_nand.c b/drivers/mtd/nand/raw/tango_nand.c
index bdb965ae7a4a7254dfb918bd6359c50f1f2bd117..021ceef4ad0acd604b4a8108864e46afb9ab96e4 100644 (file)
--- a/drivers/mtd/nand/raw/tango_nand.c
+++ b/drivers/mtd/nand/raw/tango_nand.c
@@ -550,7 +550,7 @@ static int tango_attach_chip(struct nand_chip *chip)
        struct nand_ecc_ctrl *ecc = &chip->ecc;
 
        ecc->mode = NAND_ECC_HW;
-       ecc->algo = NAND_ECC_BCH;
+       ecc->algo = NAND_ECC_ALGO_BCH;
        ecc->bytes = DIV_ROUND_UP(ecc->strength * FIELD_ORDER, BITS_PER_BYTE);
 
        ecc->read_page_raw = tango_read_page_raw;

diff --git a/drivers/mtd/nand/raw/tegra_nand.c b/drivers/mtd/nand/raw/tegra_nand.c
index 6b6212ffa01c5a5eda7012de73b42608c9c55475..0d6f3c6d6e1148cb3a807ca0fd123ccf25f25f5e 100644 (file)
--- a/drivers/mtd/nand/raw/tegra_nand.c
+++ b/drivers/mtd/nand/raw/tegra_nand.c
@@ -479,7 +479,7 @@ static void tegra_nand_hw_ecc(struct tegra_nand_controller *ctrl,
 {
        struct tegra_nand_chip *nand = to_tegra_chip(chip);
 
-       if (chip->ecc.algo == NAND_ECC_BCH && enable)
+       if (chip->ecc.algo == NAND_ECC_ALGO_BCH && enable)
                writel_relaxed(nand->bch_config, ctrl->regs + BCH_CONFIG);
        else
                writel_relaxed(0, ctrl->regs + BCH_CONFIG);
@@ -877,7 +877,7 @@ static int tegra_nand_select_strength(struct nand_chip *chip, int oobsize)
        int strength_len, bits_per_step;
 
        switch (chip->ecc.algo) {
-       case NAND_ECC_RS:
+       case NAND_ECC_ALGO_RS:
                bits_per_step = BITS_PER_STEP_RS;
                if (chip->options & NAND_IS_BOOT_MEDIUM) {
                        strength = rs_strength_bootable;
@@ -887,7 +887,7 @@ static int tegra_nand_select_strength(struct nand_chip *chip, int oobsize)
                        strength_len = ARRAY_SIZE(rs_strength);
                }
                break;
-       case NAND_ECC_BCH:
+       case NAND_ECC_ALGO_BCH:
                bits_per_step = BITS_PER_STEP_BCH;
                if (chip->options & NAND_IS_BOOT_MEDIUM) {
                        strength = bch_strength_bootable;
@@ -935,14 +935,14 @@ static int tegra_nand_attach_chip(struct nand_chip *chip)
        if (chip->options & NAND_BUSWIDTH_16)
                nand->config |= CONFIG_BUS_WIDTH_16;
 
-       if (chip->ecc.algo == NAND_ECC_UNKNOWN) {
+       if (chip->ecc.algo == NAND_ECC_ALGO_UNKNOWN) {
                if (mtd->writesize < 2048)
-                       chip->ecc.algo = NAND_ECC_RS;
+                       chip->ecc.algo = NAND_ECC_ALGO_RS;
                else
-                       chip->ecc.algo = NAND_ECC_BCH;
+                       chip->ecc.algo = NAND_ECC_ALGO_BCH;
        }
 
-       if (chip->ecc.algo == NAND_ECC_BCH && mtd->writesize < 2048) {
+       if (chip->ecc.algo == NAND_ECC_ALGO_BCH && mtd->writesize < 2048) {
                dev_err(ctrl->dev, "BCH supports 2K or 4K page size only\n");
                return -EINVAL;
        }
@@ -963,7 +963,7 @@ static int tegra_nand_attach_chip(struct nand_chip *chip)
                           CONFIG_SKIP_SPARE_SIZE_4;
 
        switch (chip->ecc.algo) {
-       case NAND_ECC_RS:
+       case NAND_ECC_ALGO_RS:
                bits_per_step = BITS_PER_STEP_RS * chip->ecc.strength;
                mtd_set_ooblayout(mtd, &tegra_nand_oob_rs_ops);
                nand->config_ecc |= CONFIG_HW_ECC | CONFIG_ECC_SEL |
@@ -984,7 +984,7 @@ static int tegra_nand_attach_chip(struct nand_chip *chip)
                        return -EINVAL;
                }
                break;
-       case NAND_ECC_BCH:
+       case NAND_ECC_ALGO_BCH:
                bits_per_step = BITS_PER_STEP_BCH * chip->ecc.strength;
                mtd_set_ooblayout(mtd, &tegra_nand_oob_bch_ops);
                nand->bch_config = BCH_ENABLE;
@@ -1013,7 +1013,7 @@ static int tegra_nand_attach_chip(struct nand_chip *chip)
        }
 
        dev_info(ctrl->dev, "Using %s with strength %d per 512 byte step\n",
-                chip->ecc.algo == NAND_ECC_BCH ? "BCH" : "RS",
+                chip->ecc.algo == NAND_ECC_ALGO_BCH ? "BCH" : "RS",
                 chip->ecc.strength);
 
        chip->ecc.bytes = DIV_ROUND_UP(bits_per_step, BITS_PER_BYTE);

diff --git a/drivers/mtd/nand/raw/xway_nand.c b/drivers/mtd/nand/raw/xway_nand.c
index 29255476afdb6054c3e22dbb4270c1435647bc0c..b279ed143b8fe70496c55f77a56851db22a799ac 100644 (file)
--- a/drivers/mtd/nand/raw/xway_nand.c
+++ b/drivers/mtd/nand/raw/xway_nand.c
@@ -181,7 +181,7 @@ static int xway_nand_probe(struct platform_device *pdev)
        data->chip.legacy.chip_delay = 30;
 
        data->chip.ecc.mode = NAND_ECC_SOFT;
-       data->chip.ecc.algo = NAND_ECC_HAMMING;
+       data->chip.ecc.algo = NAND_ECC_ALGO_HAMMING;
 
        platform_set_drvdata(pdev, data);
        nand_set_controller_data(&data->chip, data);

diff --git a/include/linux/mtd/rawnand.h b/include/linux/mtd/rawnand.h
index 1495f22b60cb43bd6595627fb2d41b02c897d5a9..8174c0c331a1e237a194b71c898dfb8308dce328 100644 (file)
--- a/include/linux/mtd/rawnand.h
+++ b/include/linux/mtd/rawnand.h
@@ -94,16 +94,16 @@ enum nand_ecc_mode {
 
 /**
  * enum nand_ecc_algo - NAND ECC algorithm
- * @NAND_ECC_UNKNOWN: Unknown algorithm
- * @NAND_ECC_HAMMING: Hamming algorithm
- * @NAND_ECC_BCH: Bose-Chaudhuri-Hocquenghem algorithm
- * @NAND_ECC_RS: Reed-Solomon algorithm
+ * @NAND_ECC_ALGO_UNKNOWN: Unknown algorithm
+ * @NAND_ECC_ALGO_HAMMING: Hamming algorithm
+ * @NAND_ECC_ALGO_BCH: Bose-Chaudhuri-Hocquenghem algorithm
+ * @NAND_ECC_ALGO_RS: Reed-Solomon algorithm
  */
 enum nand_ecc_algo {
-       NAND_ECC_UNKNOWN,
-       NAND_ECC_HAMMING,
-       NAND_ECC_BCH,
-       NAND_ECC_RS,
+       NAND_ECC_ALGO_UNKNOWN,
+       NAND_ECC_ALGO_HAMMING,
+       NAND_ECC_ALGO_BCH,
+       NAND_ECC_ALGO_RS,
 };
 
 /*