drm/i915: Parameterize ECOSKPD

Combine the separate render and blitter register definitions into a
single definition.  We already know we have some workarounds on an
upcoming platform that will need to update the ECOSKPD register for
other engines too, so this helps pave the way for that.

Cc: Jani Nikula <jani.nikula@linux.intel.com>
Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
Reviewed-by: Jani Nikula <jani.nikula@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20220111051600.3429104-4-matthew.d.roper@intel.com

diff --git a/drivers/gpu/drm/i915/gt/intel_workarounds.c b/drivers/gpu/drm/i915/gt/intel_workarounds.c
index e1f36253088918c9bedc0805e3bb9a7f80235c7b..7d87282024f5dae137561235347e9b761bf804e7 100644 (file)
--- a/drivers/gpu/drm/i915/gt/intel_workarounds.c
+++ b/drivers/gpu/drm/i915/gt/intel_workarounds.c
@@ -2126,7 +2126,7 @@ rcs_engine_wa_init(struct intel_engine_cs *engine, struct i915_wa_list *wal)
                 * they are already accustomed to from before contexts were
                 * enabled.
                 */
-               wa_add(wal, ECOSKPD,
+               wa_add(wal, ECOSKPD(RENDER_RING_BASE),
                       0, _MASKED_BIT_ENABLE(ECO_CONSTANT_BUFFER_SR_DISABLE),
                       0 /* XXX bit doesn't stick on Broadwater */,
                       true);

diff --git a/drivers/gpu/drm/i915/gvt/handlers.c b/drivers/gpu/drm/i915/gvt/handlers.c
index 3938df0db1887332f0cab1fdd80fe7119c546f2b..329d30a36f4fd639e1ac9baaa5bc700393b3787d 100644 (file)
--- a/drivers/gpu/drm/i915/gvt/handlers.c
+++ b/drivers/gpu/drm/i915/gvt/handlers.c
@@ -2877,9 +2877,9 @@ static int init_generic_mmio_info(struct intel_gvt *gvt)
 
        MMIO_D(_MMIO(0x3c), D_ALL);
        MMIO_D(_MMIO(0x860), D_ALL);
-       MMIO_D(ECOSKPD, D_ALL);
+       MMIO_D(ECOSKPD(RENDER_RING_BASE), D_ALL);
        MMIO_D(_MMIO(0x121d0), D_ALL);
-       MMIO_D(GEN6_BLITTER_ECOSKPD, D_ALL);
+       MMIO_D(ECOSKPD(BLT_RING_BASE), D_ALL);
        MMIO_D(_MMIO(0x41d0), D_ALL);
        MMIO_D(GAC_ECO_BITS, D_ALL);
        MMIO_D(_MMIO(0x6200), D_ALL);

diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index bb3f843052a9cc452a3da78743ef46bba58e1677..8bdda89bca3696c1bab9a46eab4096af9cb624f5 100644 (file)
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -2826,10 +2826,12 @@ static inline bool i915_mmio_reg_valid(i915_reg_t reg)
 #define GFX_FLSH_CNTL  _MMIO(0x2170) /* 915+ only */
 #define GFX_FLSH_CNTL_GEN6     _MMIO(0x101008)
 #define   GFX_FLSH_CNTL_EN     (1 << 0)
-#define ECOSKPD                _MMIO(0x21d0)
-#define   ECO_CONSTANT_BUFFER_SR_DISABLE REG_BIT(4)
-#define   ECO_GATING_CX_ONLY   (1 << 3)
-#define   ECO_FLIP_DONE                (1 << 0)
+#define ECOSKPD(base)          _MMIO((base) + 0x1d0)
+#define   ECO_CONSTANT_BUFFER_SR_DISABLE       REG_BIT(4)
+#define   ECO_GATING_CX_ONLY                   REG_BIT(3)
+#define   GEN6_BLITTER_FBC_NOTIFY              REG_BIT(3)
+#define   ECO_FLIP_DONE                                REG_BIT(0)
+#define   GEN6_BLITTER_LOCK_SHIFT              16
 
 #define CACHE_MODE_0_GEN7      _MMIO(0x7000) /* IVB+ */
 #define RC_OP_FLUSH_ENABLE (1 << 0)
@@ -2839,10 +2841,6 @@ static inline bool i915_mmio_reg_valid(i915_reg_t reg)
 #define   GEN8_4x4_STC_OPTIMIZATION_DISABLE    (1 << 6)
 #define   GEN9_PARTIAL_RESOLVE_IN_VC_DISABLE   (1 << 1)
 
-#define GEN6_BLITTER_ECOSKPD   _MMIO(0x221d0)
-#define   GEN6_BLITTER_LOCK_SHIFT                      16
-#define   GEN6_BLITTER_FBC_NOTIFY                      (1 << 3)
-
 #define GEN6_RC_SLEEP_PSMI_CONTROL     _MMIO(0x2050)
 #define   GEN6_PSMI_SLEEP_MSG_DISABLE  (1 << 0)
 #define   GEN12_WAIT_FOR_EVENT_POWER_DOWN_DISABLE REG_BIT(7)

diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index 161d064e0768c9fee2c7626a7c34077d5e971235..a0aefebe611f7e40fb5a4facd85486016e779954 100644 (file)
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -7845,10 +7845,12 @@ static void gen3_init_clock_gating(struct drm_i915_private *dev_priv)
        intel_uncore_write(&dev_priv->uncore, D_STATE, dstate);
 
        if (IS_PINEVIEW(dev_priv))
-               intel_uncore_write(&dev_priv->uncore, ECOSKPD, _MASKED_BIT_ENABLE(ECO_GATING_CX_ONLY));
+               intel_uncore_write(&dev_priv->uncore, ECOSKPD(RENDER_RING_BASE),
+                                  _MASKED_BIT_ENABLE(ECO_GATING_CX_ONLY));
 
        /* IIR "flip pending" means done if this bit is set */
-       intel_uncore_write(&dev_priv->uncore, ECOSKPD, _MASKED_BIT_DISABLE(ECO_FLIP_DONE));
+       intel_uncore_write(&dev_priv->uncore, ECOSKPD(RENDER_RING_BASE),
+                          _MASKED_BIT_DISABLE(ECO_FLIP_DONE));
 
        /* interrupts should cause a wake up from C3 */
        intel_uncore_write(&dev_priv->uncore, INSTPM, _MASKED_BIT_ENABLE(INSTPM_AGPBUSY_INT_EN));