wifi: rtw89: 8852c: read RX gain offset from efuse for 6GHz channels
authorPing-Ke Shih <pkshih@realtek.com>
Fri, 17 Nov 2023 02:40:27 +0000 (10:40 +0800)
committerKalle Valo <kvalo@kernel.org>
Wed, 22 Nov 2023 15:51:16 +0000 (17:51 +0200)
Read calibration values of RX gain offset from efuse, and set them to
registers to normalize RX gain for all hardware modules. Then, PHY dynamic
mechanism can get expected values to adjust hardware parameters to yield
expected performance.

Signed-off-by: Ping-Ke Shih <pkshih@realtek.com>
Signed-off-by: Kalle Valo <kvalo@kernel.org>
Link: https://lore.kernel.org/r/20231117024029.113845-5-pkshih@realtek.com
drivers/net/wireless/realtek/rtw89/core.h
drivers/net/wireless/realtek/rtw89/phy.h
drivers/net/wireless/realtek/rtw89/rtw8852c.c
drivers/net/wireless/realtek/rtw89/rtw8852c.h

index e7246eebcd997d26e599fe8a84f35e33aecae4ae..73b2e74885d0a7fc7ae1f555e6a2e40c8aff8803 100644 (file)
@@ -104,6 +104,14 @@ enum rtw89_gain_offset {
        RTW89_GAIN_OFFSET_5G_LOW,
        RTW89_GAIN_OFFSET_5G_MID,
        RTW89_GAIN_OFFSET_5G_HIGH,
+       RTW89_GAIN_OFFSET_6G_L0,
+       RTW89_GAIN_OFFSET_6G_L1,
+       RTW89_GAIN_OFFSET_6G_M0,
+       RTW89_GAIN_OFFSET_6G_M1,
+       RTW89_GAIN_OFFSET_6G_H0,
+       RTW89_GAIN_OFFSET_6G_H1,
+       RTW89_GAIN_OFFSET_6G_UH0,
+       RTW89_GAIN_OFFSET_6G_UH1,
 
        RTW89_GAIN_OFFSET_NR,
 };
index 5c85122e7bb5f4656afa75a2032acf04b8ab995d..2d9cf5c02b92cd0734a42a8ea329bf4e2cabd8e6 100644 (file)
@@ -591,6 +591,22 @@ enum rtw89_gain_offset rtw89_subband_to_gain_offset_band_of_ofdm(enum rtw89_subb
                return RTW89_GAIN_OFFSET_5G_MID;
        case RTW89_CH_5G_BAND_4:
                return RTW89_GAIN_OFFSET_5G_HIGH;
+       case RTW89_CH_6G_BAND_IDX0:
+               return RTW89_GAIN_OFFSET_6G_L0;
+       case RTW89_CH_6G_BAND_IDX1:
+               return RTW89_GAIN_OFFSET_6G_L1;
+       case RTW89_CH_6G_BAND_IDX2:
+               return RTW89_GAIN_OFFSET_6G_M0;
+       case RTW89_CH_6G_BAND_IDX3:
+               return RTW89_GAIN_OFFSET_6G_M1;
+       case RTW89_CH_6G_BAND_IDX4:
+               return RTW89_GAIN_OFFSET_6G_H0;
+       case RTW89_CH_6G_BAND_IDX5:
+               return RTW89_GAIN_OFFSET_6G_H1;
+       case RTW89_CH_6G_BAND_IDX6:
+               return RTW89_GAIN_OFFSET_6G_UH0;
+       case RTW89_CH_6G_BAND_IDX7:
+               return RTW89_GAIN_OFFSET_6G_UH1;
        }
 }
 
index 1d655ce1fd5fad6d4a41937e55ac6ee50ae14232..ea152a4613f219a48c97ec475115ebc7d99011f1 100644 (file)
@@ -426,6 +426,30 @@ static void rtw8852c_efuse_parsing_gain_offset(struct rtw89_dev *rtwdev,
        valid |= _decode_efuse_gain(map->rx_gain_5g_high,
                                    &gain->offset[RF_PATH_A][RTW89_GAIN_OFFSET_5G_HIGH],
                                    &gain->offset[RF_PATH_B][RTW89_GAIN_OFFSET_5G_HIGH]);
+       valid |= _decode_efuse_gain(map->rx_gain_6g_l0,
+                                   &gain->offset[RF_PATH_A][RTW89_GAIN_OFFSET_6G_L0],
+                                   &gain->offset[RF_PATH_B][RTW89_GAIN_OFFSET_6G_L0]);
+       valid |= _decode_efuse_gain(map->rx_gain_6g_l1,
+                                   &gain->offset[RF_PATH_A][RTW89_GAIN_OFFSET_6G_L1],
+                                   &gain->offset[RF_PATH_B][RTW89_GAIN_OFFSET_6G_L1]);
+       valid |= _decode_efuse_gain(map->rx_gain_6g_m0,
+                                   &gain->offset[RF_PATH_A][RTW89_GAIN_OFFSET_6G_M0],
+                                   &gain->offset[RF_PATH_B][RTW89_GAIN_OFFSET_6G_M0]);
+       valid |= _decode_efuse_gain(map->rx_gain_6g_m1,
+                                   &gain->offset[RF_PATH_A][RTW89_GAIN_OFFSET_6G_M1],
+                                   &gain->offset[RF_PATH_B][RTW89_GAIN_OFFSET_6G_M1]);
+       valid |= _decode_efuse_gain(map->rx_gain_6g_h0,
+                                   &gain->offset[RF_PATH_A][RTW89_GAIN_OFFSET_6G_H0],
+                                   &gain->offset[RF_PATH_B][RTW89_GAIN_OFFSET_6G_H0]);
+       valid |= _decode_efuse_gain(map->rx_gain_6g_h1,
+                                   &gain->offset[RF_PATH_A][RTW89_GAIN_OFFSET_6G_H1],
+                                   &gain->offset[RF_PATH_B][RTW89_GAIN_OFFSET_6G_H1]);
+       valid |= _decode_efuse_gain(map->rx_gain_6g_uh0,
+                                   &gain->offset[RF_PATH_A][RTW89_GAIN_OFFSET_6G_UH0],
+                                   &gain->offset[RF_PATH_B][RTW89_GAIN_OFFSET_6G_UH0]);
+       valid |= _decode_efuse_gain(map->rx_gain_6g_uh1,
+                                   &gain->offset[RF_PATH_A][RTW89_GAIN_OFFSET_6G_UH1],
+                                   &gain->offset[RF_PATH_B][RTW89_GAIN_OFFSET_6G_UH1]);
 
        gain->offset_valid = valid;
 }
index ac642808a81ff462a416f14455c89ceda0805527..77b05daedd105feeaf6c1c005505fd895cca0509 100644 (file)
@@ -73,9 +73,25 @@ struct rtw8852c_efuse {
        u8 bw40_1s_tssi_6g_a[TSSI_MCS_6G_CH_GROUP_NUM];
        u8 rsvd14[10];
        u8 bw40_1s_tssi_6g_b[TSSI_MCS_6G_CH_GROUP_NUM];
-       u8 rsvd15[110];
+       u8 rsvd15[94];
+       u8 rx_gain_6g_l0;
+       u8 rsvd16;
+       u8 rx_gain_6g_l1;
+       u8 rsvd17;
+       u8 rx_gain_6g_m0;
+       u8 rsvd18;
+       u8 rx_gain_6g_m1;
+       u8 rsvd19;
+       u8 rx_gain_6g_h0;
+       u8 rsvd20;
+       u8 rx_gain_6g_h1;
+       u8 rsvd21;
+       u8 rx_gain_6g_uh0;
+       u8 rsvd22;
+       u8 rx_gain_6g_uh1;
+       u8 rsvd23;
        u8 channel_plan_6g;
-       u8 rsvd16[71];
+       u8 rsvd24[71];
        union {
                struct rtw8852c_u_efuse u;
                struct rtw8852c_e_efuse e;