ARM: dts: Configure interconnect target module for dra7 sham

We can now probe devices with device tree only configuration using
ti-sysc interconnect target module driver. Let's configure the
module, but keep the legacy "ti,hwmods" peroperty to avoid new boot
time warnings. The legacy property will be removed in later patches
together with the legacy platform data.

Similar to am3, I could not find any documentation for the sysc
register on this one, but it seems to work just fine based on
"ti,sysc-omap3-sham" compatible style configuration.

Cc: Keerthy <j-keerthy@ti.com>
Cc: Tero Kristo <t-kristo@ti.com>
Tested-by: Tero Kristo <t-kristo@ti.com>
Reviewed-by: Tero Kristo <t-kristo@ti.com>
Tested-by: Keerthy <j-keerthy@ti.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>

diff --git a/arch/arm/boot/dts/dra7.dtsi b/arch/arm/boot/dts/dra7.dtsi
index 73e5011f531ab44b73346cd07f7f617598fd5625..bf8c10053b0432c0532c1c5da2f2e76ad93df535 100644 (file)
--- a/arch/arm/boot/dts/dra7.dtsi
+++ b/arch/arm/boot/dts/dra7.dtsi
@@ -685,15 +685,35 @@
                        clock-names = "fck";
                };
 
-               sham: sham@53100000 {
-                       compatible = "ti,omap5-sham";
+               sham_target: target-module@4b101000 {
+                       compatible = "ti,sysc-omap3-sham", "ti,sysc";
                        ti,hwmods = "sham";
-                       reg = <0x4b101000 0x300>;
-                       interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>;
-                       dmas = <&edma_xbar 119 0>;
-                       dma-names = "rx";
-                       clocks = <&l3_iclk_div>;
+                       reg = <0x4b101100 0x4>,
+                             <0x4b101110 0x4>,
+                             <0x4b101114 0x4>;
+                       reg-names = "rev", "sysc", "syss";
+                       ti,sysc-mask = <(SYSC_OMAP2_SOFTRESET |
+                                        SYSC_OMAP2_AUTOIDLE)>;
+                       ti,sysc-sidle = <SYSC_IDLE_FORCE>,
+                                       <SYSC_IDLE_NO>,
+                                       <SYSC_IDLE_SMART>;
+                       ti,syss-mask = <1>;
+                       /* Domains (P, C): l4per_pwrdm, l4sec_clkdm */
+                       clocks = <&l4sec_clkctrl DRA7_L4SEC_SHAM_CLKCTRL 0>;
                        clock-names = "fck";
+                       #address-cells = <1>;
+                       #size-cells = <1>;
+                       ranges = <0x0 0x4b101000 0x1000>;
+
+                       sham: sham@0 {
+                               compatible = "ti,omap5-sham";
+                               reg = <0 0x300>;
+                               interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>;
+                               dmas = <&edma_xbar 119 0>;
+                               dma-names = "rx";
+                               clocks = <&l3_iclk_div>;
+                               clock-names = "fck";
+                       };
                };
 
                opp_supply_mpu: opp-supply@4a003b20 {