if (!intel_dp_dsc_supports_format(intel_dp, pipe_config->output_format))
                return -EINVAL;
 
-       if (compute_pipe_bpp)
+       if (intel_dp->force_dsc_bpc && compute_pipe_bpp) {
+               pipe_bpp = intel_dp->force_dsc_bpc * 3;
+               drm_dbg_kms(&dev_priv->drm, "Input DSC BPC forced to %d\n",
+                           intel_dp->force_dsc_bpc);
+       } else if (compute_pipe_bpp) {
                pipe_bpp = intel_dp_dsc_compute_bpp(intel_dp, conn_state->max_requested_bpc);
-       else
+       } else {
                pipe_bpp = pipe_config->pipe_bpp;
-
-       if (intel_dp->force_dsc_bpc) {
-               pipe_bpp = intel_dp->force_dsc_bpc * 3;
-               drm_dbg_kms(&dev_priv->drm, "Input DSC BPP forced to %d", pipe_bpp);
        }
 
        /* Min Input BPC for ICL+ is 8 */
 
        /* enable compression if the mode doesn't fit available BW */
        drm_dbg_kms(&dev_priv->drm, "Force DSC en = %d\n", intel_dp->force_dsc_en);
        if (ret || intel_dp->force_dsc_en) {
+               /*
+                * FIXME: As bpc is hardcoded to 8, as mentioned above,
+                * WARN and ignore the debug flag force_dsc_bpc for now.
+                */
+               drm_WARN(&dev_priv->drm, intel_dp->force_dsc_bpc, "Cannot Force BPC for MST\n");
                /*
                 * Try to get at least some timeslots and then see, if
                 * we can fit there with DSC.