KVM: riscv: selftests: Add smstateen registers to get-reg-list test

We have a new smstateen registers as separate sub-type of CSR ONE_REG
interface so let us add these registers to get-reg-list test.

Signed-off-by: Anup Patel <apatel@ventanamicro.com>
Reviewed-by: Andrew Jones <ajones@ventanamicro.com>
Signed-off-by: Anup Patel <anup@brainfault.org>

diff --git a/tools/testing/selftests/kvm/riscv/get-reg-list.c b/tools/testing/selftests/kvm/riscv/get-reg-list.c
index 6cec0ef75cc7a16b0de33520eb2a3057bd993ec2..625118d53b74759a22ea42a862f6e08d55faf193 100644 (file)
--- a/tools/testing/selftests/kvm/riscv/get-reg-list.c
+++ b/tools/testing/selftests/kvm/riscv/get-reg-list.c
@@ -36,6 +36,7 @@ bool filter_reg(__u64 reg)
        case KVM_REG_RISCV_ISA_EXT | KVM_RISCV_ISA_EXT_I:
        case KVM_REG_RISCV_ISA_EXT | KVM_RISCV_ISA_EXT_M:
        case KVM_REG_RISCV_ISA_EXT | KVM_RISCV_ISA_EXT_V:
+       case KVM_REG_RISCV_ISA_EXT | KVM_RISCV_ISA_EXT_SMSTATEEN:
        case KVM_REG_RISCV_ISA_EXT | KVM_RISCV_ISA_EXT_SSAIA:
        case KVM_REG_RISCV_ISA_EXT | KVM_RISCV_ISA_EXT_SSTC:
        case KVM_REG_RISCV_ISA_EXT | KVM_RISCV_ISA_EXT_SVINVAL:
@@ -186,6 +187,8 @@ static const char *core_id_to_str(const char *prefix, __u64 id)
        "KVM_REG_RISCV_CSR_GENERAL | KVM_REG_RISCV_CSR_REG(" #csr ")"
 #define RISCV_CSR_AIA(csr) \
        "KVM_REG_RISCV_CSR_AIA | KVM_REG_RISCV_CSR_REG(" #csr ")"
+#define RISCV_CSR_SMSTATEEN(csr) \
+       "KVM_REG_RISCV_CSR_SMSTATEEN | KVM_REG_RISCV_CSR_REG(" #csr ")"
 
 static const char *general_csr_id_to_str(__u64 reg_off)
 {
@@ -243,6 +246,18 @@ static const char *aia_csr_id_to_str(__u64 reg_off)
        return NULL;
 }
 
+static const char *smstateen_csr_id_to_str(__u64 reg_off)
+{
+       /* reg_off is the offset into struct kvm_riscv_smstateen_csr */
+       switch (reg_off) {
+       case KVM_REG_RISCV_CSR_SMSTATEEN_REG(sstateen0):
+               return RISCV_CSR_SMSTATEEN(sstateen0);
+       }
+
+       TEST_FAIL("Unknown smstateen csr reg: 0x%llx", reg_off);
+       return NULL;
+}
+
 static const char *csr_id_to_str(const char *prefix, __u64 id)
 {
        __u64 reg_off = id & ~(REG_MASK | KVM_REG_RISCV_CSR);
@@ -255,6 +270,8 @@ static const char *csr_id_to_str(const char *prefix, __u64 id)
                return general_csr_id_to_str(reg_off);
        case KVM_REG_RISCV_CSR_AIA:
                return aia_csr_id_to_str(reg_off);
+       case KVM_REG_RISCV_CSR_SMSTATEEN:
+               return smstateen_csr_id_to_str(reg_off);
        }
 
        TEST_FAIL("%s: Unknown csr subtype: 0x%llx", prefix, reg_subtype);
@@ -332,6 +349,7 @@ static const char *isa_ext_id_to_str(__u64 id)
                KVM_ISA_EXT_ARR(I),
                KVM_ISA_EXT_ARR(M),
                KVM_ISA_EXT_ARR(V),
+               KVM_ISA_EXT_ARR(SMSTATEEN),
                KVM_ISA_EXT_ARR(SSAIA),
                KVM_ISA_EXT_ARR(SSTC),
                KVM_ISA_EXT_ARR(SVINVAL),
@@ -637,6 +655,11 @@ static __u64 aia_regs[] = {
        KVM_REG_RISCV | KVM_REG_SIZE_ULONG | KVM_REG_RISCV_ISA_EXT | KVM_RISCV_ISA_EXT_SSAIA,
 };
 
+static __u64 smstateen_regs[] = {
+       KVM_REG_RISCV | KVM_REG_SIZE_ULONG | KVM_REG_RISCV_CSR | KVM_REG_RISCV_CSR_SMSTATEEN | KVM_REG_RISCV_CSR_SMSTATEEN_REG(sstateen0),
+       KVM_REG_RISCV | KVM_REG_SIZE_ULONG | KVM_REG_RISCV_ISA_EXT | KVM_RISCV_ISA_EXT_SMSTATEEN,
+};
+
 static __u64 fp_f_regs[] = {
        KVM_REG_RISCV | KVM_REG_SIZE_U32 | KVM_REG_RISCV_FP_F | KVM_REG_RISCV_FP_F_REG(f[0]),
        KVM_REG_RISCV | KVM_REG_SIZE_U32 | KVM_REG_RISCV_FP_F | KVM_REG_RISCV_FP_F_REG(f[1]),
@@ -744,6 +767,8 @@ static __u64 fp_d_regs[] = {
        {"zihpm", .feature = KVM_RISCV_ISA_EXT_ZIHPM, .regs = zihpm_regs, .regs_n = ARRAY_SIZE(zihpm_regs),}
 #define AIA_REGS_SUBLIST \
        {"aia", .feature = KVM_RISCV_ISA_EXT_SSAIA, .regs = aia_regs, .regs_n = ARRAY_SIZE(aia_regs),}
+#define SMSTATEEN_REGS_SUBLIST \
+       {"smstateen", .feature = KVM_RISCV_ISA_EXT_SMSTATEEN, .regs = smstateen_regs, .regs_n = ARRAY_SIZE(smstateen_regs),}
 #define FP_F_REGS_SUBLIST \
        {"fp_f", .feature = KVM_RISCV_ISA_EXT_F, .regs = fp_f_regs, \
                .regs_n = ARRAY_SIZE(fp_f_regs),}
@@ -871,6 +896,14 @@ static struct vcpu_reg_list aia_config = {
        },
 };
 
+static struct vcpu_reg_list smstateen_config = {
+       .sublists = {
+       BASE_SUBLIST,
+       SMSTATEEN_REGS_SUBLIST,
+       {0},
+       },
+};
+
 static struct vcpu_reg_list fp_f_config = {
        .sublists = {
        BASE_SUBLIST,
@@ -903,6 +936,7 @@ struct vcpu_reg_list *vcpu_configs[] = {
        &zifencei_config,
        &zihpm_config,
        &aia_config,
+       &smstateen_config,
        &fp_f_config,
        &fp_d_config,
 };