arm64: dts: bitmain: Add clock controller support for BM1880 SoC

Add clock controller support for Bitmain BM1880 SoC.

Link: https://lore.kernel.org/r/20200114040311.6599-2-manivannan.sadhasivam@linaro.org
Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
Signed-off-by: Olof Johansson <olof@lixom.net>

diff --git a/arch/arm64/boot/dts/bitmain/bm1880.dtsi b/arch/arm64/boot/dts/bitmain/bm1880.dtsi
index d65453f99a993a1d4ad7a5132798b1a109663b34..8471662413daee66d295b59f55bf77d838077b13 100644 (file)
--- a/arch/arm64/boot/dts/bitmain/bm1880.dtsi
+++ b/arch/arm64/boot/dts/bitmain/bm1880.dtsi
@@ -4,6 +4,7 @@
  * Author: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
  */
 
+#include <dt-bindings/clock/bm1880-clock.h>
 #include <dt-bindings/interrupt-controller/arm-gic.h>
 #include <dt-bindings/reset/bitmain,bm1880-reset.h>
 
@@ -66,6 +67,12 @@
                             <GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>;
        };
 
+       osc: osc {
+               compatible = "fixed-clock";
+               clock-frequency = <25000000>;
+               #clock-cells = <0>;
+       };
+
        soc {
                compatible = "simple-bus";
                #address-cells = <2>;
@@ -94,6 +101,15 @@
                                reg = <0x400 0x120>;
                        };
 
+                       clk: clock-controller@e8 {
+                               compatible = "bitmain,bm1880-clk";
+                               reg = <0xe8 0x0c>, <0x800 0xb0>;
+                               reg-names = "pll", "sys";
+                               clocks = <&osc>;
+                               clock-names = "osc";
+                               #clock-cells = <1>;
+                       };
+
                        rst: reset-controller@c00 {
                                compatible = "bitmain,bm1880-reset";
                                reg = <0xc00 0x8>;