ARM: dts: Configure system timers for am335x
authorTony Lindgren <tony@atomide.com>
Thu, 7 May 2020 16:59:31 +0000 (09:59 -0700)
committerTony Lindgren <tony@atomide.com>
Tue, 19 May 2020 16:38:03 +0000 (09:38 -0700)
We can now init system timers using the dmtimer and 32k counter
based on only devicetree data and drivers/clocksource timers.
Let's configure the clocksource and clockevent, and drop the old
unused platform data.

As we're just dropping platform data, and the early platform data
init is based on the custom ti,hwmods property, we want to drop
both the platform data and ti,hwmods property in a single patch.

Since the dmtimer can use both 32k clock and system clock as the
source, let's also configure the SoC specific default values. The
board specific dts files can reconfigure these with assigned-clocks
and assigned-clock-parents as needed.

Cc: devicetree@vger.kernel.org
Cc: Grygorii Strashko <grygorii.strashko@ti.com>
Cc: Keerthy <j-keerthy@ti.com>
Cc: Lokesh Vutla <lokeshvutla@ti.com>
Cc: Rob Herring <robh@kernel.org>
Cc: Tero Kristo <t-kristo@ti.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>
arch/arm/boot/dts/am33xx-l4.dtsi
arch/arm/boot/dts/am33xx.dtsi
arch/arm/mach-omap2/board-generic.c
arch/arm/mach-omap2/omap_hwmod_33xx_43xx_ipblock_data.c
arch/arm/mach-omap2/omap_hwmod_33xx_data.c

index 5ed7f3c58c0f2bd326fa84780655ffb976fa8f27..7ff11d6bf0f2be0d98a481376a702721617142ba 100644 (file)
                        };
                };
 
-               target-module@31000 {                   /* 0x44e31000, ap 25 40.0 */
+               timer1_target: target-module@31000 {    /* 0x44e31000, ap 25 40.0 */
                        compatible = "ti,sysc-omap2-timer", "ti,sysc";
-                       ti,hwmods = "timer1";
                        reg = <0x31000 0x4>,
                              <0x31010 0x4>,
                              <0x31014 0x4>;
                        };
                };
 
-               target-module@40000 {                   /* 0x48040000, ap 22 1e.0 */
+               timer2_target: target-module@40000 {    /* 0x48040000, ap 22 1e.0 */
                        compatible = "ti,sysc-omap4-timer", "ti,sysc";
-                       ti,hwmods = "timer2";
                        reg = <0x40000 0x4>,
                              <0x40010 0x4>,
                              <0x40014 0x4>;
index a35f5052d76f698d224082159a85c331f87f999f..3b177c9c4412feea18d83281f2b14869ee2e3066 100644 (file)
                #reset-cells = <1>;
        };
 };
+
+/* Preferred always-on timer for clocksource */
+&timer1_target {
+       ti,no-reset-on-init;
+       ti,no-idle;
+       timer@0 {
+               assigned-clocks = <&timer1_fck>;
+               assigned-clock-parents = <&sys_clkin_ck>;
+       };
+};
+
+/* Preferred timer for clockevent */
+&timer2_target {
+       ti,no-reset-on-init;
+       ti,no-idle;
+       timer@0 {
+               assigned-clocks = <&timer2_fck>;
+               assigned-clock-parents = <&sys_clkin_ck>;
+       };
+};
index c6f7dcf13a1543bce3b486b594712079e3ee6517..cce9523eaa779b897d6ead8ec5ae42786e8b28c8 100644 (file)
@@ -236,7 +236,7 @@ DT_MACHINE_START(AM33XX_DT, "Generic AM33XX (Flattened Device Tree)")
        .init_early     = am33xx_init_early,
        .init_machine   = omap_generic_init,
        .init_late      = am33xx_init_late,
-       .init_time      = omap3_gptimer_timer_init,
+       .init_time      = omap_init_time_of,
        .dt_compat      = am33xx_boards_compat,
        .restart        = am33xx_restart,
 MACHINE_END
index dca5a3a7b97c198c29733ee9ef97e40b07b5f7f4..99c63333848827f0de5aa6caebb83bcf23e6097e 100644 (file)
@@ -367,12 +367,10 @@ struct omap_hwmod am33xx_timer2_hwmod = {
 
 static void omap_hwmod_am33xx_clkctrl(void)
 {
-       CLKCTRL(am33xx_timer2_hwmod, AM33XX_CM_PER_TIMER2_CLKCTRL_OFFSET);
        CLKCTRL(am33xx_smartreflex0_hwmod,
                AM33XX_CM_WKUP_SMARTREFLEX0_CLKCTRL_OFFSET);
        CLKCTRL(am33xx_smartreflex1_hwmod,
                AM33XX_CM_WKUP_SMARTREFLEX1_CLKCTRL_OFFSET);
-       CLKCTRL(am33xx_timer1_hwmod, AM33XX_CM_WKUP_TIMER1_CLKCTRL_OFFSET);
        CLKCTRL(am33xx_rtc_hwmod, AM33XX_CM_RTC_RTC_CLKCTRL_OFFSET);
        PRCM_FLAGS(am33xx_rtc_hwmod, HWMOD_OMAP4_ZERO_CLKCTRL_OFFSET);
        CLKCTRL(am33xx_gpmc_hwmod, AM33XX_CM_PER_GPMC_CLKCTRL_OFFSET);
index c64b735c8accc39c10b7e8fe05aa2fa661776445..3cf9c4c90b18654f7ee14966682af2fcfa30768d 100644 (file)
@@ -265,14 +265,6 @@ static struct omap_hwmod_ocp_if am33xx_l4_wkup__control = {
        .user           = OCP_USER_MPU,
 };
 
-/* l4 wkup -> timer1 */
-static struct omap_hwmod_ocp_if am33xx_l4_wkup__timer1 = {
-       .master         = &am33xx_l4_wkup_hwmod,
-       .slave          = &am33xx_timer1_hwmod,
-       .clk            = "dpll_core_m4_div2_ck",
-       .user           = OCP_USER_MPU,
-};
-
 static struct omap_hwmod_ocp_if *am33xx_hwmod_ocp_ifs[] __initdata = {
        &am33xx_l3_main__emif,
        &am33xx_mpu__l3_main,
@@ -291,9 +283,7 @@ static struct omap_hwmod_ocp_if *am33xx_hwmod_ocp_ifs[] __initdata = {
        &am33xx_l4_wkup__control,
        &am33xx_l4_wkup__smartreflex0,
        &am33xx_l4_wkup__smartreflex1,
-       &am33xx_l4_wkup__timer1,
        &am33xx_l4_wkup__rtc,
-       &am33xx_l4_ls__timer2,
        &am33xx_l3_s__gpmc,
        &am33xx_l3_main__ocmc,
        NULL,