.clkr.hw.init = &(struct clk_init_data){
                .name = "gcc_blsp1_qup1_i2c_apps_clk_src",
                .parent_data = gcc_parents_0,
-               .num_parents = 4,
+               .num_parents = ARRAY_SIZE(gcc_parents_0),
                .ops = &clk_rcg2_ops,
        },
 };
        .clkr.hw.init = &(struct clk_init_data){
                .name = "gcc_blsp1_qup1_spi_apps_clk_src",
                .parent_data = gcc_parents_0,
-               .num_parents = 4,
+               .num_parents = ARRAY_SIZE(gcc_parents_0),
                .ops = &clk_rcg2_ops,
        },
 };
        .clkr.hw.init = &(struct clk_init_data){
                .name = "gcc_blsp1_qup2_i2c_apps_clk_src",
                .parent_data = gcc_parents_0,
-               .num_parents = 4,
+               .num_parents = ARRAY_SIZE(gcc_parents_0),
                .ops = &clk_rcg2_ops,
        },
 };
        .clkr.hw.init = &(struct clk_init_data){
                .name = "gcc_blsp1_qup2_spi_apps_clk_src",
                .parent_data = gcc_parents_0,
-               .num_parents = 4,
+               .num_parents = ARRAY_SIZE(gcc_parents_0),
                .ops = &clk_rcg2_ops,
        },
 };
        .clkr.hw.init = &(struct clk_init_data){
                .name = "gcc_blsp1_qup3_i2c_apps_clk_src",
                .parent_data = gcc_parents_0,
-               .num_parents = 4,
+               .num_parents = ARRAY_SIZE(gcc_parents_0),
                .ops = &clk_rcg2_ops,
        },
 };
        .clkr.hw.init = &(struct clk_init_data){
                .name = "gcc_blsp1_qup3_spi_apps_clk_src",
                .parent_data = gcc_parents_0,
-               .num_parents = 4,
+               .num_parents = ARRAY_SIZE(gcc_parents_0),
                .ops = &clk_rcg2_ops,
        },
 };
        .clkr.hw.init = &(struct clk_init_data){
                .name = "gcc_blsp1_qup4_i2c_apps_clk_src",
                .parent_data = gcc_parents_0,
-               .num_parents = 4,
+               .num_parents = ARRAY_SIZE(gcc_parents_0),
                .ops = &clk_rcg2_ops,
        },
 };
        .clkr.hw.init = &(struct clk_init_data){
                .name = "gcc_blsp1_qup4_spi_apps_clk_src",
                .parent_data = gcc_parents_0,
-               .num_parents = 4,
+               .num_parents = ARRAY_SIZE(gcc_parents_0),
                .ops = &clk_rcg2_ops,
        },
 };
        .clkr.hw.init = &(struct clk_init_data){
                .name = "gcc_blsp1_uart1_apps_clk_src",
                .parent_data = gcc_parents_0,
-               .num_parents = 4,
+               .num_parents = ARRAY_SIZE(gcc_parents_0),
                .ops = &clk_rcg2_ops,
        },
 };
        .clkr.hw.init = &(struct clk_init_data){
                .name = "gcc_blsp1_uart2_apps_clk_src",
                .parent_data = gcc_parents_0,
-               .num_parents = 4,
+               .num_parents = ARRAY_SIZE(gcc_parents_0),
                .ops = &clk_rcg2_ops,
        },
 };
        .clkr.hw.init = &(struct clk_init_data){
                .name = "gcc_blsp1_uart3_apps_clk_src",
                .parent_data = gcc_parents_0,
-               .num_parents = 4,
+               .num_parents = ARRAY_SIZE(gcc_parents_0),
                .ops = &clk_rcg2_ops,
        },
 };
        .clkr.hw.init = &(struct clk_init_data){
                .name = "gcc_blsp1_uart4_apps_clk_src",
                .parent_data = gcc_parents_0,
-               .num_parents = 4,
+               .num_parents = ARRAY_SIZE(gcc_parents_0),
                .ops = &clk_rcg2_ops,
        },
 };
        .clkr.hw.init = &(struct clk_init_data){
                .name = "gcc_cpuss_ahb_clk_src",
                .parent_data = gcc_parents_0_ao,
-               .num_parents = 4,
+               .num_parents = ARRAY_SIZE(gcc_parents_0_ao),
                .ops = &clk_rcg2_ops,
        },
 };
        .clkr.hw.init = &(struct clk_init_data){
                .name = "gcc_cpuss_rbcpr_clk_src",
                .parent_data = gcc_parents_0_ao,
-               .num_parents = 4,
+               .num_parents = ARRAY_SIZE(gcc_parents_0_ao),
                .ops = &clk_rcg2_ops,
        },
 };
        .clkr.hw.init = &(struct clk_init_data){
                .name = "gcc_emac_clk_src",
                .parent_data = gcc_parents_5,
-               .num_parents = 5,
+               .num_parents = ARRAY_SIZE(gcc_parents_5),
                .ops = &clk_rcg2_ops,
        },
 };
        .clkr.hw.init = &(struct clk_init_data){
                .name = "gcc_emac_ptp_clk_src",
                .parent_data = gcc_parents_2,
-               .num_parents = 6,
+               .num_parents = ARRAY_SIZE(gcc_parents_2),
                .ops = &clk_rcg2_ops,
        },
 };
        .clkr.hw.init = &(struct clk_init_data){
                .name = "gcc_gp1_clk_src",
                .parent_data = gcc_parents_3,
-               .num_parents = 5,
+               .num_parents = ARRAY_SIZE(gcc_parents_3),
                .ops = &clk_rcg2_ops,
        },
 };
        .clkr.hw.init = &(struct clk_init_data){
                .name = "gcc_gp2_clk_src",
                .parent_data = gcc_parents_3,
-               .num_parents = 5,
+               .num_parents = ARRAY_SIZE(gcc_parents_3),
                .ops = &clk_rcg2_ops,
        },
 };
        .clkr.hw.init = &(struct clk_init_data){
                .name = "gcc_gp3_clk_src",
                .parent_data = gcc_parents_3,
-               .num_parents = 5,
+               .num_parents = ARRAY_SIZE(gcc_parents_3),
                .ops = &clk_rcg2_ops,
        },
 };
        .clkr.hw.init = &(struct clk_init_data){
                .name = "gcc_pcie_aux_phy_clk_src",
                .parent_data = gcc_parents_4,
-               .num_parents = 3,
+               .num_parents = ARRAY_SIZE(gcc_parents_4),
                .ops = &clk_rcg2_ops,
        },
 };
        .clkr.hw.init = &(struct clk_init_data){
                .name = "gcc_pcie_rchng_phy_clk_src",
                .parent_data = gcc_parents_3,
-               .num_parents = 5,
+               .num_parents = ARRAY_SIZE(gcc_parents_3),
                .ops = &clk_rcg2_ops,
        },
 };
        .clkr.hw.init = &(struct clk_init_data){
                .name = "gcc_pdm2_clk_src",
                .parent_data = gcc_parents_0,
-               .num_parents = 4,
+               .num_parents = ARRAY_SIZE(gcc_parents_0),
                .ops = &clk_rcg2_ops,
        },
 };
        .clkr.hw.init = &(struct clk_init_data){
                .name = "gcc_sdcc1_apps_clk_src",
                .parent_data = gcc_parents_0,
-               .num_parents = 4,
+               .num_parents = ARRAY_SIZE(gcc_parents_0),
                .ops = &clk_rcg2_ops,
        },
 };
        .clkr.hw.init = &(struct clk_init_data){
                .name = "gcc_usb30_master_clk_src",
                .parent_data = gcc_parents_0,
-               .num_parents = 4,
+               .num_parents = ARRAY_SIZE(gcc_parents_0),
                .ops = &clk_rcg2_ops,
        },
 };
        .clkr.hw.init = &(struct clk_init_data){
                .name = "gcc_usb30_mock_utmi_clk_src",
                .parent_data = gcc_parents_0,
-               .num_parents = 4,
+               .num_parents = ARRAY_SIZE(gcc_parents_0),
                .ops = &clk_rcg2_ops,
        },
 };
        .clkr.hw.init = &(struct clk_init_data){
                .name = "gcc_usb3_phy_aux_clk_src",
                .parent_data = gcc_parents_4,
-               .num_parents = 3,
+               .num_parents = ARRAY_SIZE(gcc_parents_4),
                .ops = &clk_rcg2_ops,
        },
 };