drm/i915: move chv_dpll_md and bxt_phy_grc to display sub-struct under state

Move the display related members to the struct drm_i915_private display
sub-struct. Put them under "state", as they are related to storing
values that aren't readable from the hardware, to appease the state
checker.

Signed-off-by: Jani Nikula <jani.nikula@intel.com>
Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20230117143946.2426043-3-jani.nikula@intel.com

diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
index 9b73663a0499c66b7d8d1dea73a97831bc7cb36a..c38a54efedbe82aed5b488d573d69ded0c4ca5bf 100644 (file)
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -3241,7 +3241,7 @@ static bool i9xx_get_pipe_config(struct intel_crtc *crtc,
        if (DISPLAY_VER(dev_priv) >= 4) {
                /* No way to read it out on pipes B and C */
                if (IS_CHERRYVIEW(dev_priv) && crtc->pipe != PIPE_A)
-                       tmp = dev_priv->chv_dpll_md[crtc->pipe];
+                       tmp = dev_priv->display.state.chv_dpll_md[crtc->pipe];
                else
                        tmp = intel_de_read(dev_priv, DPLL_MD(crtc->pipe));
                pipe_config->pixel_multiplier =

diff --git a/drivers/gpu/drm/i915/display/intel_display_core.h b/drivers/gpu/drm/i915/display/intel_display_core.h
index c0eb753112d5aaf3eecd295a5d5a366217a7ddbd..24c792d44b8f8268363e3a31940e535156fd9836 100644 (file)
--- a/drivers/gpu/drm/i915/display/intel_display_core.h
+++ b/drivers/gpu/drm/i915/display/intel_display_core.h
@@ -441,6 +441,16 @@ struct intel_display {
                u8 phy_failed_calibration;
        } snps;
 
+       struct {
+               /*
+                * Shadows for CHV DPLL_MD regs to keep the state
+                * checker somewhat working in the presence hardware
+                * crappiness (can't read out DPLL_MD for pipes B & C).
+                */
+               u32 chv_dpll_md[I915_MAX_PIPES];
+               u32 bxt_phy_grc;
+       } state;
+
        struct {
                /* ordered wq for modesets */
                struct workqueue_struct *modeset;

diff --git a/drivers/gpu/drm/i915/display/intel_dpio_phy.c b/drivers/gpu/drm/i915/display/intel_dpio_phy.c
index 7eb7440b31803f7b46f6c82f102bd152f42683b8..565c06de2432dbc2b53d4147077d3372e02fd319 100644 (file)
--- a/drivers/gpu/drm/i915/display/intel_dpio_phy.c
+++ b/drivers/gpu/drm/i915/display/intel_dpio_phy.c
@@ -376,7 +376,7 @@ static void _bxt_ddi_phy_init(struct drm_i915_private *dev_priv,
        if (bxt_ddi_phy_is_enabled(dev_priv, phy)) {
                /* Still read out the GRC value for state verification */
                if (phy_info->rcomp_phy != -1)
-                       dev_priv->bxt_phy_grc = bxt_get_grc(dev_priv, phy);
+                       dev_priv->display.state.bxt_phy_grc = bxt_get_grc(dev_priv, phy);
 
                if (bxt_ddi_phy_verify_state(dev_priv, phy)) {
                        drm_dbg(&dev_priv->drm, "DDI PHY %d already enabled, "
@@ -442,8 +442,9 @@ static void _bxt_ddi_phy_init(struct drm_i915_private *dev_priv,
                 * the corresponding calibrated value from PHY1, and disable
                 * the automatic calibration on PHY0.
                 */
-               val = dev_priv->bxt_phy_grc = bxt_get_grc(dev_priv,
-                                                         phy_info->rcomp_phy);
+               val = bxt_get_grc(dev_priv, phy_info->rcomp_phy);
+               dev_priv->display.state.bxt_phy_grc = val;
+
                grc_code = val << GRC_CODE_FAST_SHIFT |
                           val << GRC_CODE_SLOW_SHIFT |
                           val;
@@ -568,7 +569,7 @@ bool bxt_ddi_phy_verify_state(struct drm_i915_private *dev_priv,
                           "BXT_PORT_CL2CM_DW6(%d)", phy);
 
        if (phy_info->rcomp_phy != -1) {
-               u32 grc_code = dev_priv->bxt_phy_grc;
+               u32 grc_code = dev_priv->display.state.bxt_phy_grc;
 
                grc_code = grc_code << GRC_CODE_FAST_SHIFT |
                           grc_code << GRC_CODE_SLOW_SHIFT |

diff --git a/drivers/gpu/drm/i915/display/intel_dpll.c b/drivers/gpu/drm/i915/display/intel_dpll.c
index c236aafe9be0151c1f455a03ae93e3ae960fcf16..4e9c18be7e1fd1f0b8d20d95424b8e200020c25a 100644 (file)
--- a/drivers/gpu/drm/i915/display/intel_dpll.c
+++ b/drivers/gpu/drm/i915/display/intel_dpll.c
@@ -1910,7 +1910,7 @@ void chv_enable_pll(const struct intel_crtc_state *crtc_state)
                intel_de_write(dev_priv, DPLL_MD(PIPE_B),
                               crtc_state->dpll_hw_state.dpll_md);
                intel_de_write(dev_priv, CBR4_VLV, 0);
-               dev_priv->chv_dpll_md[pipe] = crtc_state->dpll_hw_state.dpll_md;
+               dev_priv->display.state.chv_dpll_md[pipe] = crtc_state->dpll_hw_state.dpll_md;
 
                /*
                 * DPLLB VGA mode also seems to cause problems.

diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 4e24d6f597d51c94c93f94a14ac5cb9b08c2c18b..bdb853bb668ac502b56e932f5b69dfb9077c8ca3 100644 (file)
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -308,14 +308,6 @@ struct drm_i915_private {
 
        struct i915_gpu_error gpu_error;
 
-       /*
-        * Shadows for CHV DPLL_MD regs to keep the state
-        * checker somewhat working in the presence hardware
-        * crappiness (can't read out DPLL_MD for pipes B & C).
-        */
-       u32 chv_dpll_md[I915_MAX_PIPES];
-       u32 bxt_phy_grc;
-
        u32 suspend_count;
        struct i915_suspend_saved_registers regfile;
        struct vlv_s0ix_state *vlv_s0ix_state;