riscv: dts: starfive: Add cpu scaling for JH7110 SoC

Add the operating-points-v2 to support cpu scaling on StarFive JH7110 SoC.
It supports up to 4 cpu frequency loads.

Signed-off-by: Mason Huo <mason.huo@starfivetech.com>
Signed-off-by: Conor Dooley <conor.dooley@microchip.com>

diff --git a/arch/riscv/boot/dts/starfive/jh7110-starfive-visionfive-2.dtsi b/arch/riscv/boot/dts/starfive/jh7110-starfive-visionfive-2.dtsi
index 9714da5550d70558ee31037bcd0b57561dfd2960..fa0061eb33a75fbcf089c4349b836a63edb64b4e 100644 (file)
--- a/arch/riscv/boot/dts/starfive/jh7110-starfive-visionfive-2.dtsi
+++ b/arch/riscv/boot/dts/starfive/jh7110-starfive-visionfive-2.dtsi
@@ -230,3 +230,19 @@
        pinctrl-0 = <&uart0_pins>;
        status = "okay";
 };
+
+&U74_1 {
+       cpu-supply = <&vdd_cpu>;
+};
+
+&U74_2 {
+       cpu-supply = <&vdd_cpu>;
+};
+
+&U74_3 {
+       cpu-supply = <&vdd_cpu>;
+};
+
+&U74_4 {
+       cpu-supply = <&vdd_cpu>;
+};

diff --git a/arch/riscv/boot/dts/starfive/jh7110.dtsi b/arch/riscv/boot/dts/starfive/jh7110.dtsi
index 03c6cc49fa229e080aaf731e61276ff95585cdaf..ec2e70011a73673669babb53323b9ee5240355c0 100644 (file)
--- a/arch/riscv/boot/dts/starfive/jh7110.dtsi
+++ b/arch/riscv/boot/dts/starfive/jh7110.dtsi
@@ -53,6 +53,9 @@
                        next-level-cache = <&ccache>;
                        riscv,isa = "rv64imafdc_zba_zbb";
                        tlb-split;
+                       operating-points-v2 = <&cpu_opp>;
+                       clocks = <&syscrg JH7110_SYSCLK_CPU_CORE>;
+                       clock-names = "cpu";
 
                        cpu1_intc: interrupt-controller {
                                compatible = "riscv,cpu-intc";
@@ -79,6 +82,9 @@
                        next-level-cache = <&ccache>;
                        riscv,isa = "rv64imafdc_zba_zbb";
                        tlb-split;
+                       operating-points-v2 = <&cpu_opp>;
+                       clocks = <&syscrg JH7110_SYSCLK_CPU_CORE>;
+                       clock-names = "cpu";
 
                        cpu2_intc: interrupt-controller {
                                compatible = "riscv,cpu-intc";
@@ -105,6 +111,9 @@
                        next-level-cache = <&ccache>;
                        riscv,isa = "rv64imafdc_zba_zbb";
                        tlb-split;
+                       operating-points-v2 = <&cpu_opp>;
+                       clocks = <&syscrg JH7110_SYSCLK_CPU_CORE>;
+                       clock-names = "cpu";
 
                        cpu3_intc: interrupt-controller {
                                compatible = "riscv,cpu-intc";
@@ -131,6 +140,9 @@
                        next-level-cache = <&ccache>;
                        riscv,isa = "rv64imafdc_zba_zbb";
                        tlb-split;
+                       operating-points-v2 = <&cpu_opp>;
+                       clocks = <&syscrg JH7110_SYSCLK_CPU_CORE>;
+                       clock-names = "cpu";
 
                        cpu4_intc: interrupt-controller {
                                compatible = "riscv,cpu-intc";
@@ -164,6 +176,27 @@
                };
        };
 
+       cpu_opp: opp-table-0 {
+                       compatible = "operating-points-v2";
+                       opp-shared;
+                       opp-375000000 {
+                                       opp-hz = /bits/ 64 <375000000>;
+                                       opp-microvolt = <800000>;
+                       };
+                       opp-500000000 {
+                                       opp-hz = /bits/ 64 <500000000>;
+                                       opp-microvolt = <800000>;
+                       };
+                       opp-750000000 {
+                                       opp-hz = /bits/ 64 <750000000>;
+                                       opp-microvolt = <800000>;
+                       };
+                       opp-1500000000 {
+                                       opp-hz = /bits/ 64 <1500000000>;
+                                       opp-microvolt = <1040000>;
+                       };
+       };
+
        gmac0_rgmii_rxin: gmac0-rgmii-rxin-clock {
                compatible = "fixed-clock";
                clock-output-names = "gmac0_rgmii_rxin";