iommus = <&smmu TEGRA186_SID_HOST1X>;
 
+               /* Context isolation domains */
+               iommu-map = <
+                       0 &smmu TEGRA186_SID_HOST1X_CTX0 1
+                       1 &smmu TEGRA186_SID_HOST1X_CTX1 1
+                       2 &smmu TEGRA186_SID_HOST1X_CTX2 1
+                       3 &smmu TEGRA186_SID_HOST1X_CTX3 1
+                       4 &smmu TEGRA186_SID_HOST1X_CTX4 1
+                       5 &smmu TEGRA186_SID_HOST1X_CTX5 1
+                       6 &smmu TEGRA186_SID_HOST1X_CTX6 1
+                       7 &smmu TEGRA186_SID_HOST1X_CTX7 1>;
+
                dpaux1: dpaux@15040000 {
                        compatible = "nvidia,tegra186-dpaux";
                        reg = <0x15040000 0x10000>;
 
                        interconnect-names = "dma-mem";
                        iommus = <&smmu TEGRA194_SID_HOST1X>;
 
+                       /* Context isolation domains */
+                       iommu-map = <
+                               0 &smmu TEGRA194_SID_HOST1X_CTX0 1
+                               1 &smmu TEGRA194_SID_HOST1X_CTX1 1
+                               2 &smmu TEGRA194_SID_HOST1X_CTX2 1
+                               3 &smmu TEGRA194_SID_HOST1X_CTX3 1
+                               4 &smmu TEGRA194_SID_HOST1X_CTX4 1
+                               5 &smmu TEGRA194_SID_HOST1X_CTX5 1
+                               6 &smmu TEGRA194_SID_HOST1X_CTX6 1
+                               7 &smmu TEGRA194_SID_HOST1X_CTX7 1>;
+
                        nvdec@15140000 {
                                compatible = "nvidia,tegra194-nvdec";
                                reg = <0x15140000 0x00040000>;