C(RGF_USER_CLKS_CTL_0, BIT_USER_CLKS_RST_PWGD);
 
+       /* enable fix for HW bug related to the SA/DA swap in AP Rx */
+       S(RGF_DMA_OFUL_NID_0, BIT_DMA_OFUL_NID_0_RX_EXT_TR_EN |
+         BIT_DMA_OFUL_NID_0_RX_EXT_A3_SRC);
+
        wil_dbg_misc(wil, "Reset completed in %d ms\n", delay * RST_DELAY);
        return 0;
 }
 
        }
 }
 
-/*
- * Fast swap in place between 2 registers
- */
-static void wil_swap_u16(u16 *a, u16 *b)
-{
-       *a ^= *b;
-       *b ^= *a;
-       *a ^= *b;
-}
-
-static void wil_swap_ethaddr(void *data)
-{
-       struct ethhdr *eth = data;
-       u16 *s = (u16 *)eth->h_source;
-       u16 *d = (u16 *)eth->h_dest;
-
-       wil_swap_u16(s++, d++);
-       wil_swap_u16(s++, d++);
-       wil_swap_u16(s, d);
-}
-
 /**
  * reap 1 frame from @swhead
  *
        unsigned int sz = mtu_max + ETH_HLEN;
        u16 dmalen;
        u8 ftype;
-       u8 ds_bits;
        int cid;
        struct wil_net_stats *stats;
 
                 */
        }
 
-       ds_bits = wil_rxdesc_ds_bits(d);
-       if (ds_bits == 1) {
-               /*
-                * HW bug - in ToDS mode, i.e. Rx on AP side,
-                * addresses get swapped
-                */
-               wil_swap_ethaddr(skb->data);
-       }
-
        return skb;
 }
 
 
        #define BIT_DMA_ITR_CNT_CRL_CLR         BIT(3)
        #define BIT_DMA_ITR_CNT_CRL_REACH_TRSH  BIT(4)
 
+/* Offload control (Sparrow B0+) */
+#define RGF_DMA_OFUL_NID_0             (0x881cd4)
+       #define BIT_DMA_OFUL_NID_0_RX_EXT_TR_EN         BIT(0)
+       #define BIT_DMA_OFUL_NID_0_TX_EXT_TR_EN         BIT(1)
+       #define BIT_DMA_OFUL_NID_0_RX_EXT_A3_SRC        BIT(2)
+       #define BIT_DMA_OFUL_NID_0_TX_EXT_A3_SRC        BIT(3)
+
 /* New (sparrow v2+) interrupt moderation control */
 #define RGF_DMA_ITR_TX_DESQ_NO_MOD             (0x881d40)
 #define RGF_DMA_ITR_TX_CNT_TRSH                        (0x881d34)