scsi: ufs: ufs-exynos: Change pclk available max value

To support 167MHz PCLK, we need to adjust the maximum value.

Link: https://lore.kernel.org/r/20211018124216.153072-4-chanho61.park@samsung.com
Reviewed-by: Alim Akhtar <alim.akhtar@samsung.com>
Reviewed-by: Inki Dae <inki.dae@samsung.com>
Signed-off-by: Chanho Park <chanho61.park@samsung.com>
Signed-off-by: Martin K. Petersen <martin.petersen@oracle.com>

diff --git a/drivers/scsi/ufs/ufs-exynos.h b/drivers/scsi/ufs/ufs-exynos.h
index dadf4fd10dd8050251edba28635853e706339d41..0a31f77a5f48da08e774accd083ba7fcf9b10dc6 100644 (file)
--- a/drivers/scsi/ufs/ufs-exynos.h
+++ b/drivers/scsi/ufs/ufs-exynos.h
@@ -99,7 +99,7 @@ struct exynos_ufs;
 #define PA_HIBERN8TIME_VAL     0x20
 
 #define PCLK_AVAIL_MIN 70000000
-#define PCLK_AVAIL_MAX 133000000
+#define PCLK_AVAIL_MAX 167000000
 
 struct exynos_ufs_uic_attr {
        /* TX Attributes */