drm/i915/pvc: Implement recommended caching policy

As per the performance tuning guide, set the HOSTCACHEEN bit to
implement the recommended caching policy on PVC.

Signed-off-by: Wayne Boyer <wayne.boyer@intel.com>
Reviewed-by: Matt Roper <matthew.d.roper@intel.com>
Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20221130170723.2460014-1-wayne.boyer@intel.com

diff --git a/drivers/gpu/drm/i915/gt/intel_gt_regs.h b/drivers/gpu/drm/i915/gt/intel_gt_regs.h
index 6caf2d8deb985a44f6fd380e8a4da038a3050efb..fa12edafd4e228980c171ca7ad320b9337456190 100644 (file)
--- a/drivers/gpu/drm/i915/gt/intel_gt_regs.h
+++ b/drivers/gpu/drm/i915/gt/intel_gt_regs.h
@@ -972,6 +972,7 @@
 #define   GEN7_L3AGDIS                         (1 << 19)
 
 #define XEHPC_LNCFMISCCFGREG0                  _MMIO(0xb01c)
+#define   XEHPC_HOSTCACHEEN                    REG_BIT(1)
 #define   XEHPC_OVRLSCCC                       REG_BIT(0)
 
 #define GEN7_L3CNTLREG2                                _MMIO(0xb020)

diff --git a/drivers/gpu/drm/i915/gt/intel_workarounds.c b/drivers/gpu/drm/i915/gt/intel_workarounds.c
index cafa7b9145b59b1b38cf09cde8c48f5a24ef869a..ff63b3859e6fc73a6cfb41d4e1daab91eb35b429 100644 (file)
--- a/drivers/gpu/drm/i915/gt/intel_workarounds.c
+++ b/drivers/gpu/drm/i915/gt/intel_workarounds.c
@@ -2906,6 +2906,7 @@ add_render_compute_tuning_settings(struct drm_i915_private *i915,
        if (IS_PONTEVECCHIO(i915)) {
                wa_write(wal, XEHPC_L3SCRUB,
                         SCRUB_CL_DWNGRADE_SHARED | SCRUB_RATE_4B_PER_CLK);
+               wa_masked_en(wal, XEHPC_LNCFMISCCFGREG0, XEHPC_HOSTCACHEEN);
        }
 
        if (IS_DG2(i915)) {