Merge tag 'for-upstream' of https://gitlab.com/bonzini/qemu into staging

* qdev: second part of Property cleanups
* rust: second part of QOM rework
* rust: callbacks wrapper
* rust: pl011 bugfixes
* kvm: cleanup errors in kvm_convert_memory()

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* tag 'for-upstream' of https://gitlab.com/bonzini/qemu: (42 commits)
  rust: pl011: simplify handling of the FIFO enabled bit in LCR
  rust: pl011: fix migration stream
  rust: pl011: extend registers to 32 bits
  rust: pl011: fix break errors and definition of Data struct
  rust: pl011: always use reset() method on registers
  rust: pl011: match break logic of C version
  rust: pl011: fix declaration of LineControl bits
  target/i386: Reset TSCs of parked vCPUs too on VM reset
  kvm: consistently return 0/-errno from kvm_convert_memory
  rust: qemu-api: add a module to wrap functions and zero-sized closures
  rust: qom: add initial subset of methods on Object
  rust: qom: add casting functionality
  rust: tests: allow writing more than one test
  bql: add a "mock" BQL for Rust unit tests
  rust: re-export C types from qemu-api submodules
  rust: rename qemu-api modules to follow C code a bit more
  rust: qom: add possibility of overriding unparent
  rust: qom: put class_init together from multiple ClassInitImpl<>
  Constify all opaque Property pointers
  hw/core/qdev-properties: Constify Property argument to PropertyInfo.print
  ...

Signed-off-by: Stefan Hajnoczi <stefanha@redhat.com>

diff --cc hw/intc/arm_gicv3_its.c
Simple merge

diff --cc hw/intc/loongarch_extioi_common.c
index e50431f124a3a09ebe2de7e099edc60089aa3676,0000000000000000000000000000000000000000..e4c1cc3c9867e8e8fa751ffd5eacb74c6d8bcdae
mode 100644,000000..100644
--- 1/hw/intc/loongarch_extioi_common.c
--- /dev/null
+++ b/hw/intc/loongarch_extioi_common.c
@@@ -1,113 -1,0 +1,112 @@@
-     DEFINE_PROP_END_OF_LIST(),
 +/* SPDX-License-Identifier: GPL-2.0-or-later */
 +/*
 + * Loongson extioi interrupt controller emulation
 + * Copyright (C) 2024 Loongson Technology Corporation Limited
 + */
 +#include "qemu/osdep.h"
 +#include "qemu/module.h"
 +#include "qapi/error.h"
 +#include "hw/qdev-properties.h"
 +#include "hw/intc/loongarch_extioi_common.h"
 +#include "migration/vmstate.h"
 +
 +static void loongarch_extioi_common_realize(DeviceState *dev, Error **errp)
 +{
 +    LoongArchExtIOICommonState *s = (LoongArchExtIOICommonState *)dev;
 +
 +    if (s->num_cpu == 0) {
 +        error_setg(errp, "num-cpu must be at least 1");
 +        return;
 +    }
 +}
 +
 +static int loongarch_extioi_common_pre_save(void *opaque)
 +{
 +    LoongArchExtIOICommonState *s = (LoongArchExtIOICommonState *)opaque;
 +    LoongArchExtIOICommonClass *lecc = LOONGARCH_EXTIOI_COMMON_GET_CLASS(s);
 +
 +    if (lecc->pre_save) {
 +        return lecc->pre_save(s);
 +    }
 +
 +    return 0;
 +}
 +
 +static int loongarch_extioi_common_post_load(void *opaque, int version_id)
 +{
 +    LoongArchExtIOICommonState *s = (LoongArchExtIOICommonState *)opaque;
 +    LoongArchExtIOICommonClass *lecc = LOONGARCH_EXTIOI_COMMON_GET_CLASS(s);
 +
 +    if (lecc->post_load) {
 +        return lecc->post_load(s, version_id);
 +    }
 +
 +    return 0;
 +}
 +
 +static const VMStateDescription vmstate_extioi_core = {
 +    .name = "extioi-core",
 +    .version_id = 1,
 +    .minimum_version_id = 1,
 +    .fields = (const VMStateField[]) {
 +        VMSTATE_UINT32_ARRAY(coreisr, ExtIOICore, EXTIOI_IRQS_GROUP_COUNT),
 +        VMSTATE_END_OF_LIST()
 +    }
 +};
 +
 +static const VMStateDescription vmstate_loongarch_extioi = {
 +    .name = "loongarch.extioi",
 +    .version_id = 3,
 +    .minimum_version_id = 3,
 +    .pre_save  = loongarch_extioi_common_pre_save,
 +    .post_load = loongarch_extioi_common_post_load,
 +    .fields = (const VMStateField[]) {
 +        VMSTATE_UINT32_ARRAY(bounce, LoongArchExtIOICommonState,
 +                             EXTIOI_IRQS_GROUP_COUNT),
 +        VMSTATE_UINT32_ARRAY(nodetype, LoongArchExtIOICommonState,
 +                             EXTIOI_IRQS_NODETYPE_COUNT / 2),
 +        VMSTATE_UINT32_ARRAY(enable, LoongArchExtIOICommonState,
 +                             EXTIOI_IRQS / 32),
 +        VMSTATE_UINT32_ARRAY(isr, LoongArchExtIOICommonState,
 +                             EXTIOI_IRQS / 32),
 +        VMSTATE_UINT32_ARRAY(ipmap, LoongArchExtIOICommonState,
 +                             EXTIOI_IRQS_IPMAP_SIZE / 4),
 +        VMSTATE_UINT32_ARRAY(coremap, LoongArchExtIOICommonState,
 +                             EXTIOI_IRQS / 4),
 +        VMSTATE_STRUCT_VARRAY_POINTER_UINT32(cpu, LoongArchExtIOICommonState,
 +                             num_cpu, vmstate_extioi_core, ExtIOICore),
 +        VMSTATE_UINT32(features, LoongArchExtIOICommonState),
 +        VMSTATE_UINT32(status, LoongArchExtIOICommonState),
 +        VMSTATE_END_OF_LIST()
 +    }
 +};
 +
 +static const Property extioi_properties[] = {
 +    DEFINE_PROP_UINT32("num-cpu", LoongArchExtIOICommonState, num_cpu, 1),
 +    DEFINE_PROP_BIT("has-virtualization-extension", LoongArchExtIOICommonState,
 +                    features, EXTIOI_HAS_VIRT_EXTENSION, 0),
 +};
 +
 +static void loongarch_extioi_common_class_init(ObjectClass *klass, void *data)
 +{
 +    DeviceClass *dc = DEVICE_CLASS(klass);
 +    LoongArchExtIOICommonClass *lecc = LOONGARCH_EXTIOI_COMMON_CLASS(klass);
 +
 +    device_class_set_parent_realize(dc, loongarch_extioi_common_realize,
 +                                    &lecc->parent_realize);
 +    device_class_set_props(dc, extioi_properties);
 +    dc->vmsd = &vmstate_loongarch_extioi;
 +}
 +
 +static const TypeInfo loongarch_extioi_common_types[] = {
 +    {
 +        .name               = TYPE_LOONGARCH_EXTIOI_COMMON,
 +        .parent             = TYPE_SYS_BUS_DEVICE,
 +        .instance_size      = sizeof(LoongArchExtIOICommonState),
 +        .class_size         = sizeof(LoongArchExtIOICommonClass),
 +        .class_init         = loongarch_extioi_common_class_init,
 +        .abstract           = true,
 +    }
 +};
 +
 +DEFINE_TYPES(loongarch_extioi_common_types)

diff --cc hw/intc/loongarch_pic_common.c
index bcb6b7b3fca12992550fc343330547c7aa124148,0000000000000000000000000000000000000000..e7f541db4b55d3c83dbea7469c614363f409c324
mode 100644,000000..100644
--- 1/hw/intc/loongarch_pic_common.c
--- /dev/null
+++ b/hw/intc/loongarch_pic_common.c
@@@ -1,97 -1,0 +1,96 @@@
-     DEFINE_PROP_END_OF_LIST(),
 +/* SPDX-License-Identifier: GPL-2.0-or-later */
 +/*
 + * QEMU Loongson 7A1000 I/O interrupt controller.
 + * Copyright (C) 2024 Loongson Technology Corporation Limited
 + */
 +
 +#include "qemu/osdep.h"
 +#include "qapi/error.h"
 +#include "hw/intc/loongarch_pic_common.h"
 +#include "hw/qdev-properties.h"
 +#include "migration/vmstate.h"
 +
 +static int loongarch_pic_pre_save(void *opaque)
 +{
 +    LoongArchPICCommonState *s = (LoongArchPICCommonState *)opaque;
 +    LoongArchPICCommonClass *lpcc = LOONGARCH_PIC_COMMON_GET_CLASS(s);
 +
 +    if (lpcc->pre_save) {
 +        return lpcc->pre_save(s);
 +    }
 +
 +    return 0;
 +}
 +
 +static int loongarch_pic_post_load(void *opaque, int version_id)
 +{
 +    LoongArchPICCommonState *s = (LoongArchPICCommonState *)opaque;
 +    LoongArchPICCommonClass *lpcc = LOONGARCH_PIC_COMMON_GET_CLASS(s);
 +
 +    if (lpcc->post_load) {
 +        return lpcc->post_load(s, version_id);
 +    }
 +
 +    return 0;
 +}
 +
 +static void loongarch_pic_common_realize(DeviceState *dev, Error **errp)
 +{
 +    LoongArchPICCommonState *s = LOONGARCH_PIC_COMMON(dev);
 +
 +    if (!s->irq_num || s->irq_num  > VIRT_PCH_PIC_IRQ_NUM) {
 +        error_setg(errp, "Invalid 'pic_irq_num'");
 +        return;
 +    }
 +}
 +
 +static const Property loongarch_pic_common_properties[] = {
 +    DEFINE_PROP_UINT32("pch_pic_irq_num", LoongArchPICCommonState, irq_num, 0),
 +};
 +
 +static const VMStateDescription vmstate_loongarch_pic_common = {
 +    .name = "loongarch_pch_pic",
 +    .version_id = 1,
 +    .minimum_version_id = 1,
 +    .pre_save  = loongarch_pic_pre_save,
 +    .post_load = loongarch_pic_post_load,
 +    .fields = (const VMStateField[]) {
 +        VMSTATE_UINT64(int_mask, LoongArchPICCommonState),
 +        VMSTATE_UINT64(htmsi_en, LoongArchPICCommonState),
 +        VMSTATE_UINT64(intedge, LoongArchPICCommonState),
 +        VMSTATE_UINT64(intclr, LoongArchPICCommonState),
 +        VMSTATE_UINT64(auto_crtl0, LoongArchPICCommonState),
 +        VMSTATE_UINT64(auto_crtl1, LoongArchPICCommonState),
 +        VMSTATE_UINT8_ARRAY(route_entry, LoongArchPICCommonState, 64),
 +        VMSTATE_UINT8_ARRAY(htmsi_vector, LoongArchPICCommonState, 64),
 +        VMSTATE_UINT64(last_intirr, LoongArchPICCommonState),
 +        VMSTATE_UINT64(intirr, LoongArchPICCommonState),
 +        VMSTATE_UINT64(intisr, LoongArchPICCommonState),
 +        VMSTATE_UINT64(int_polarity, LoongArchPICCommonState),
 +        VMSTATE_END_OF_LIST()
 +    }
 +};
 +
 +static void loongarch_pic_common_class_init(ObjectClass *klass, void *data)
 +{
 +    DeviceClass *dc = DEVICE_CLASS(klass);
 +    LoongArchPICCommonClass *lpcc = LOONGARCH_PIC_COMMON_CLASS(klass);
 +
 +    device_class_set_parent_realize(dc, loongarch_pic_common_realize,
 +                                    &lpcc->parent_realize);
 +    device_class_set_props(dc, loongarch_pic_common_properties);
 +    dc->vmsd = &vmstate_loongarch_pic_common;
 +}
 +
 +static const TypeInfo loongarch_pic_common_types[] = {
 +    {
 +        .name               = TYPE_LOONGARCH_PIC_COMMON,
 +        .parent             = TYPE_SYS_BUS_DEVICE,
 +        .instance_size      = sizeof(LoongArchPICCommonState),
 +        .class_size         = sizeof(LoongArchPICCommonClass),
 +        .class_init         = loongarch_pic_common_class_init,
 +        .abstract           = true,
 +    }
 +};
 +
 +DEFINE_TYPES(loongarch_pic_common_types)