drm/msm: update LANE_CTRL register value from default value

LANE_CTRL register in latest version of DSI controller (v2.2)
has additional functionality introduced to enable/disable HS
signalling with default value set to enabled. To accommodate this
change, LANE_CTRL register should be read and bit wise ORed to enable
non continuous clock mode. Without this change, if register is written
directly, HS signalling will be disabled resulting in black screen.

Changes in v1:
	-Update LANE_CTRL register value
Changes in v2:
	-Changing commit message accordingly.

Signed-off-by: Harigovindan P <harigovi@codeaurora.org>
Signed-off-by: Rob Clark <robdclark@chromium.org>

diff --git a/drivers/gpu/drm/msm/dsi/dsi_host.c b/drivers/gpu/drm/msm/dsi/dsi_host.c
index 33c8d6dac5a9b1ad14afebe397f6a42bed5919aa..11ae5b8444c329f17b3193a22631e0df875fe707 100644 (file)
--- a/drivers/gpu/drm/msm/dsi/dsi_host.c
+++ b/drivers/gpu/drm/msm/dsi/dsi_host.c
@@ -833,7 +833,7 @@ static void dsi_ctrl_config(struct msm_dsi_host *msm_host, bool enable,
        u32 flags = msm_host->mode_flags;
        enum mipi_dsi_pixel_format mipi_fmt = msm_host->format;
        const struct msm_dsi_cfg_handler *cfg_hnd = msm_host->cfg_hnd;
-       u32 data = 0;
+       u32 data = 0, lane_ctrl = 0;
 
        if (!enable) {
                dsi_write(msm_host, REG_DSI_CTRL, 0);
@@ -921,9 +921,11 @@ static void dsi_ctrl_config(struct msm_dsi_host *msm_host, bool enable,
        dsi_write(msm_host, REG_DSI_LANE_SWAP_CTRL,
                  DSI_LANE_SWAP_CTRL_DLN_SWAP_SEL(msm_host->dlane_swap));
 
-       if (!(flags & MIPI_DSI_CLOCK_NON_CONTINUOUS))
+       if (!(flags & MIPI_DSI_CLOCK_NON_CONTINUOUS)) {
+               lane_ctrl = dsi_read(msm_host, REG_DSI_LANE_CTRL);
                dsi_write(msm_host, REG_DSI_LANE_CTRL,
-                       DSI_LANE_CTRL_CLKLN_HS_FORCE_REQUEST);
+                       lane_ctrl | DSI_LANE_CTRL_CLKLN_HS_FORCE_REQUEST);
+       }
 
        data |= DSI_CTRL_ENABLE;