clk: renesas: rcar-gen2: Rename vsp1-(sy|rt) clocks to vsp(s|r)
authorLad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Mon, 31 Aug 2020 18:37:22 +0000 (19:37 +0100)
committerGeert Uytterhoeven <geert+renesas@glider.be>
Fri, 4 Sep 2020 07:42:01 +0000 (09:42 +0200)
VSP1 instances VSPS (which stands for "VSP Standard") and VSPR (which
stands for "VSP for Resizing") were wrongly named as "vsp1-sy" and
"vsp1-rt". The clock section in the SoC datasheets misunderstood the
abbreviations as meaning VSP System and VSP Realtime, and named the
corresponding clocks VSP1(SY) and VSP1(RT). This mistake has been
carried over to the kernel code.

This patch fixes this by renaming the clock names to "vsps" and "vspr".

Inspired from commit 79ea9934b8df ("ARM: shmobile: r8a7790: Rename
VSP1_(SY|RT) clocks to VSP1_(S|R)")

Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Link: https://lore.kernel.org/r/20200831183722.8165-1-prabhakar.mahadev-lad.rj@bp.renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
drivers/clk/renesas/r8a7743-cpg-mssr.c
drivers/clk/renesas/r8a7745-cpg-mssr.c
drivers/clk/renesas/r8a77470-cpg-mssr.c
drivers/clk/renesas/r8a7790-cpg-mssr.c
drivers/clk/renesas/r8a7791-cpg-mssr.c
drivers/clk/renesas/r8a7792-cpg-mssr.c
drivers/clk/renesas/r8a7794-cpg-mssr.c

index c01d9af2525a181a3614a40b2444138126310fa5..0bba12a48d22b96c441c4a097bfabfde62181205 100644 (file)
@@ -92,7 +92,7 @@ static const struct mssr_mod_clk r8a7743_mod_clks[] __initconst = {
        DEF_MOD("tmu0",                  125,   R8A7743_CLK_CP),
        DEF_MOD("vsp1du1",               127,   R8A7743_CLK_ZS),
        DEF_MOD("vsp1du0",               128,   R8A7743_CLK_ZS),
-       DEF_MOD("vsp1-sy",               131,   R8A7743_CLK_ZS),
+       DEF_MOD("vsps",                  131,   R8A7743_CLK_ZS),
        DEF_MOD("scifa2",                202,   R8A7743_CLK_MP),
        DEF_MOD("scifa1",                203,   R8A7743_CLK_MP),
        DEF_MOD("scifa0",                204,   R8A7743_CLK_MP),
index 493874e5ebeeb6bb50aef7cb780289d406ea5c8f..dc4a64e8dfb5aba58806688d7c8bca9f32f90abc 100644 (file)
@@ -90,7 +90,7 @@ static const struct mssr_mod_clk r8a7745_mod_clks[] __initconst = {
        DEF_MOD("cmt0",                  124,   R8A7745_CLK_R),
        DEF_MOD("tmu0",                  125,   R8A7745_CLK_CP),
        DEF_MOD("vsp1du0",               128,   R8A7745_CLK_ZS),
-       DEF_MOD("vsp1-sy",               131,   R8A7745_CLK_ZS),
+       DEF_MOD("vsps",                  131,   R8A7745_CLK_ZS),
        DEF_MOD("scifa2",                202,   R8A7745_CLK_MP),
        DEF_MOD("scifa1",                203,   R8A7745_CLK_MP),
        DEF_MOD("scifa0",                204,   R8A7745_CLK_MP),
index d81ae65f0d188aa4339a4b0a83207c609304fd8b..f3d6e65011d7dba4fa64f47c4ed9f7bbf6630da6 100644 (file)
@@ -85,7 +85,7 @@ static const struct mssr_mod_clk r8a77470_mod_clks[] __initconst = {
        DEF_MOD("tmu2",                  122,   R8A77470_CLK_P),
        DEF_MOD("cmt0",                  124,   R8A77470_CLK_R),
        DEF_MOD("vsp1du0",               128,   R8A77470_CLK_ZS),
-       DEF_MOD("vsp1-sy",               131,   R8A77470_CLK_ZS),
+       DEF_MOD("vsps",                  131,   R8A77470_CLK_ZS),
        DEF_MOD("msiof2",                205,   R8A77470_CLK_MP),
        DEF_MOD("msiof1",                208,   R8A77470_CLK_MP),
        DEF_MOD("sys-dmac1",             218,   R8A77470_CLK_ZS),
index c57cb93f831589f85eed013f616d99ceadf5c740..f7d233e0c142bbaa49ba579e4921e73e39b2483e 100644 (file)
@@ -108,8 +108,8 @@ static const struct mssr_mod_clk r8a7790_mod_clks[] __initconst = {
        DEF_MOD("tmu0",                  125,   R8A7790_CLK_CP),
        DEF_MOD("vsp1du1",               127,   R8A7790_CLK_ZS),
        DEF_MOD("vsp1du0",               128,   R8A7790_CLK_ZS),
-       DEF_MOD("vsp1-rt",               130,   R8A7790_CLK_ZS),
-       DEF_MOD("vsp1-sy",               131,   R8A7790_CLK_ZS),
+       DEF_MOD("vspr",                  130,   R8A7790_CLK_ZS),
+       DEF_MOD("vsps",                  131,   R8A7790_CLK_ZS),
        DEF_MOD("scifa2",                202,   R8A7790_CLK_MP),
        DEF_MOD("scifa1",                203,   R8A7790_CLK_MP),
        DEF_MOD("scifa0",                204,   R8A7790_CLK_MP),
index 65702debcabbf654a23ad9922415b3c5f95d77b5..a0de784868da325c3686f4bf0899175d951afe08 100644 (file)
@@ -102,7 +102,7 @@ static const struct mssr_mod_clk r8a7791_mod_clks[] __initconst = {
        DEF_MOD("tmu0",                  125,   R8A7791_CLK_CP),
        DEF_MOD("vsp1du1",               127,   R8A7791_CLK_ZS),
        DEF_MOD("vsp1du0",               128,   R8A7791_CLK_ZS),
-       DEF_MOD("vsp1-sy",               131,   R8A7791_CLK_ZS),
+       DEF_MOD("vsps",                  131,   R8A7791_CLK_ZS),
        DEF_MOD("scifa2",                202,   R8A7791_CLK_MP),
        DEF_MOD("scifa1",                203,   R8A7791_CLK_MP),
        DEF_MOD("scifa0",                204,   R8A7791_CLK_MP),
index cf8b84a3a06052fbdacf63e6975e0b60bc6b4456..77af250876a56fa503cf75d324d242cd40ad2df2 100644 (file)
@@ -88,7 +88,7 @@ static const struct mssr_mod_clk r8a7792_mod_clks[] __initconst = {
        DEF_MOD("tmu0",                  125,   R8A7792_CLK_CP),
        DEF_MOD("vsp1du1",               127,   R8A7792_CLK_ZS),
        DEF_MOD("vsp1du0",               128,   R8A7792_CLK_ZS),
-       DEF_MOD("vsp1-sy",               131,   R8A7792_CLK_ZS),
+       DEF_MOD("vsps",                  131,   R8A7792_CLK_ZS),
        DEF_MOD("msiof1",                208,   R8A7792_CLK_MP),
        DEF_MOD("sys-dmac1",             218,   R8A7792_CLK_ZS),
        DEF_MOD("sys-dmac0",             219,   R8A7792_CLK_ZS),
index c1948693c5c1c499b8262b12925c74a2ef1fb8e3..4d7fa26a72c99870d1787df525e3dd88b24e77ec 100644 (file)
@@ -97,7 +97,7 @@ static const struct mssr_mod_clk r8a7794_mod_clks[] __initconst = {
        DEF_MOD("cmt0",                  124,   R8A7794_CLK_R),
        DEF_MOD("tmu0",                  125,   R8A7794_CLK_CP),
        DEF_MOD("vsp1du0",               128,   R8A7794_CLK_ZS),
-       DEF_MOD("vsp1-sy",               131,   R8A7794_CLK_ZS),
+       DEF_MOD("vsps",                  131,   R8A7794_CLK_ZS),
        DEF_MOD("scifa2",                202,   R8A7794_CLK_MP),
        DEF_MOD("scifa1",                203,   R8A7794_CLK_MP),
        DEF_MOD("scifa0",                204,   R8A7794_CLK_MP),