staging: iio: frequency: ad9834: Fix alignment for DMA safety

____cacheline_aligned is an insufficient guarantee for non-coherent DMA
on platforms with 128 byte cachelines above L1.  Switch to the updated
IIO_DMA_MINALIGN definition.

Signed-off-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
Reviewed-by: Andy Shevchenko <andy.shevchenko@gmail.com>
Link: https://lore.kernel.org/r/20220807151218.656881-3-jic23@kernel.org

diff --git a/drivers/staging/iio/frequency/ad9834.c b/drivers/staging/iio/frequency/ad9834.c
index 94b131ef8a22c0942260207b8f3dac7e9d7b7b9a..2b4267a87e65e153e9b5fa55cf17d3b9e3677720 100644 (file)
--- a/drivers/staging/iio/frequency/ad9834.c
+++ b/drivers/staging/iio/frequency/ad9834.c
@@ -83,7 +83,7 @@ struct ad9834_state {
         * DMA (thus cache coherency maintenance) requires the
         * transfer buffers to live in their own cache lines.
         */
-       __be16                          data ____cacheline_aligned;
+       __be16                          data __aligned(IIO_DMA_MINALIGN);
        __be16                          freq_data[2];
 };