drm/msm/dpu: drop DPU_INTF_TE feature flag

Replace the only user of the DPU_INTF_TE feature flag with the direct
DPU version comparison.

Reviewed-by: Marijn Suijten <marijn.suijten@somainline.org>
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Reviewed-by: Stephen Boyd <swboyd@chromium.org>
Patchwork: https://patchwork.freedesktop.org/patch/555540/
Link: https://lore.kernel.org/r/20230904020454.2945667-7-dmitry.baryshkov@linaro.org

diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_cmd.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_cmd.c
index cab7a32d1c29b815af17ec9ca3767d1aff23156d..0b52e6d205ee4701785e60c5037a50d5b6b89b7f 100644 (file)
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_cmd.c
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_cmd.c
@@ -778,8 +778,9 @@ struct dpu_encoder_phys *dpu_encoder_phys_cmd_init(
        phys_enc->intf_mode = INTF_MODE_CMD;
        cmd_enc->stream_sel = 0;
 
-       phys_enc->has_intf_te = test_bit(DPU_INTF_TE,
-                                        &phys_enc->hw_intf->cap->features);
+       /* DPU before 5.0 use PINGPONG for TE handling */
+       if (phys_enc->dpu_kms->catalog->mdss_ver->core_major_ver >= 5)
+               phys_enc->has_intf_te = true;
 
        atomic_set(&cmd_enc->pending_vblank_cnt, 0);
        init_waitqueue_head(&cmd_enc->pending_vblank_wq);

diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c
index d89bdd0dd27ae0fcaeec53acabbd65460fd740f2..a1aada6307808c247efc197abaeff4197fc4c73c 100644 (file)
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c
@@ -100,7 +100,6 @@
 
 #define INTF_SC7180_MASK \
        (BIT(DPU_INTF_INPUT_CTRL) | \
-        BIT(DPU_INTF_TE) | \
         BIT(DPU_INTF_STATUS_SUPPORTED) | \
         BIT(DPU_DATA_HCTL_EN))
 

diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h
index 4f7e4a23775e59570e518caafa281740a9124b7f..df024e10d3a32b900a868d565a2d89d31299b1a6 100644 (file)
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h
@@ -158,7 +158,6 @@ enum {
  * INTF sub-blocks
  * @DPU_INTF_INPUT_CTRL             Supports the setting of pp block from which
  *                                  pixel data arrives to this INTF
- * @DPU_INTF_TE                     INTF block has TE configuration support
  * @DPU_DATA_HCTL_EN                Allows data to be transferred at different rate
  *                                  than video timing
  * @DPU_INTF_STATUS_SUPPORTED       INTF block has INTF_STATUS register
@@ -166,7 +165,6 @@ enum {
  */
 enum {
        DPU_INTF_INPUT_CTRL = 0x1,
-       DPU_INTF_TE,
        DPU_DATA_HCTL_EN,
        DPU_INTF_STATUS_SUPPORTED,
        DPU_INTF_MAX