ARM: dts: am335x-sancloud-bbe-lite: New devicetree

This adds support for the Sancloud BBE Lite which shares a common
hardware base with the non-Lite version of the BBE.

Signed-off-by: Paul Barker <paul.barker@sancloud.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>

diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile
index 863347b6b65e46278a4dca16235f9cb367e2becc..8da525e7f0ab2f0929d14c0a0208ab6bd6d86a47 100644 (file)
--- a/arch/arm/boot/dts/Makefile
+++ b/arch/arm/boot/dts/Makefile
@@ -843,6 +843,7 @@ dtb-$(CONFIG_SOC_AM33XX) += \
        am335x-pocketbeagle.dtb \
        am335x-regor-rdk.dtb \
        am335x-sancloud-bbe.dtb \
+       am335x-sancloud-bbe-lite.dtb \
        am335x-shc.dtb \
        am335x-sbc-t335.dtb \
        am335x-sl50.dtb \

diff --git a/arch/arm/boot/dts/am335x-sancloud-bbe-lite.dts b/arch/arm/boot/dts/am335x-sancloud-bbe-lite.dts
new file mode 100644 (file)
index 0000000..d6ef193
--- /dev/null
+++ b/arch/arm/boot/dts/am335x-sancloud-bbe-lite.dts
@@ -0,0 +1,50 @@
+// SPDX-License-Identifier: GPL-2.0-only
+/*
+ * Copyright (C) 2012 Texas Instruments Incorporated - http://www.ti.com/
+ * Copyright (C) 2021 SanCloud Ltd
+ */
+/dts-v1/;
+
+#include "am33xx.dtsi"
+#include "am335x-bone-common.dtsi"
+#include "am335x-boneblack-common.dtsi"
+#include "am335x-sancloud-bbe-common.dtsi"
+
+/ {
+       model = "SanCloud BeagleBone Enhanced Lite";
+       compatible = "sancloud,am335x-boneenhanced",
+                    "ti,am335x-bone-black",
+                    "ti,am335x-bone",
+                    "ti,am33xx";
+};
+
+&am33xx_pinmux {
+       bb_spi0_pins: pinmux_bb_spi0_pins {
+               pinctrl-single,pins = <
+                       AM33XX_PADCONF(AM335X_PIN_SPI0_SCLK, PIN_INPUT, MUX_MODE0)
+                       AM33XX_PADCONF(AM335X_PIN_SPI0_D0, PIN_INPUT, MUX_MODE0)
+                       AM33XX_PADCONF(AM335X_PIN_SPI0_D1, PIN_INPUT, MUX_MODE0)
+                       AM33XX_PADCONF(AM335X_PIN_SPI0_CS0, PIN_INPUT, MUX_MODE0)
+               >;
+       };
+};
+
+&spi0 {
+       #address-cells = <1>;
+       #size-cells = <0>;
+
+       status = "okay";
+       pinctrl-names = "default";
+       pinctrl-0 = <&bb_spi0_pins>;
+
+       channel@0 {
+               #address-cells = <1>;
+               #size-cells = <0>;
+
+               compatible = "micron,spi-authenta";
+
+               reg = <0>;
+               spi-max-frequency = <16000000>;
+               spi-cpha;
+       };
+};