arm64: dts: qcom: sdm630: add ICE registers and clocks

Add the registers and clock for the Inline Crypto Engine (ICE) to the
device tree node for the sdhci-msm host controller on sdm630.  This
allows sdhci-msm to support inline encryption on sdm630.

Signed-off-by: Eric Biggers <ebiggers@google.com>
Link: https://lore.kernel.org/r/20210121090140.326380-9-ebiggers@kernel.org
[bjorn: Changed indentation]
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>

diff --git a/arch/arm64/boot/dts/qcom/sdm630.dtsi b/arch/arm64/boot/dts/qcom/sdm630.dtsi
index 37d5cc32f6b62d09fa66103dc1fac85a7ec8b36e..f91a928466c3bbd8553179c9307cea89944a1d62 100644 (file)
--- a/arch/arm64/boot/dts/qcom/sdm630.dtsi
+++ b/arch/arm64/boot/dts/qcom/sdm630.dtsi
@@ -808,17 +808,19 @@
                sdhc_1: sdhci@c0c4000 {
                        compatible = "qcom,sdm630-sdhci", "qcom,sdhci-msm-v5";
                        reg = <0x0c0c4000 0x1000>,
-                               <0x0c0c5000 0x1000>;
-                       reg-names = "hc", "cqhci";
+                             <0x0c0c5000 0x1000>,
+                             <0x0c0c8000 0x8000>;
+                       reg-names = "hc", "cqhci", "ice";
 
                        interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>,
                                        <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>;
                        interrupt-names = "hc_irq", "pwr_irq";
 
                        clocks = <&gcc GCC_SDCC1_APPS_CLK>,
-                                       <&gcc GCC_SDCC1_AHB_CLK>,
-                                       <&xo_board>;
-                       clock-names = "core", "iface", "xo";
+                                <&gcc GCC_SDCC1_AHB_CLK>,
+                                <&xo_board>,
+                                <&gcc GCC_SDCC1_ICE_CORE_CLK>;
+                       clock-names = "core", "iface", "xo", "ice";
 
                        pinctrl-names = "default", "sleep";
                        pinctrl-0 = <&sdc1_clk_on &sdc1_cmd_on &sdc1_data_on &sdc1_rclk_on>;