drm/msm/dpu: fix DSC 1.2 block lengths
authorDmitry Baryshkov <dmitry.baryshkov@linaro.org>
Wed, 2 Aug 2023 18:36:54 +0000 (21:36 +0300)
committerDmitry Baryshkov <dmitry.baryshkov@linaro.org>
Thu, 3 Aug 2023 11:17:32 +0000 (14:17 +0300)
All DSC_BLK_1_2 declarations incorrectly pass 0x29c as the block length.
This includes the common block itself, enc subblocks and some empty
space around. Change that to pass 0x4 instead, the length of common
register block itself.

Fixes: 0d1b10c63346 ("drm/msm/dpu: add DSC 1.2 hw blocks for relevant chipsets")
Reported-by: Ryan McCann <quic_rmccann@quicinc.com>
Reviewed-by: Abhinav Kumar <quic_abhinavk@quicinc.com>
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Reviewed-by: Marijn Suijten <marijn.suijten@somainline.org>
Patchwork: https://patchwork.freedesktop.org/patch/550998/
Link: https://lore.kernel.org/r/20230802183655.4188640-1-dmitry.baryshkov@linaro.org
drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_7_0_sm8350.h
drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_7_2_sc7280.h
drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_0_sc8280xp.h
drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_1_sm8450.h
drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_9_0_sm8550.h

index c906b6864b5e99a7ea557bd63617a0ef0e0b3a02..f8d16f9bf528d87de9a4bea738e9cae50a3c5d90 100644 (file)
@@ -283,22 +283,22 @@ static const struct dpu_merge_3d_cfg sm8350_merge_3d[] = {
 static const struct dpu_dsc_cfg sm8350_dsc[] = {
        {
                .name = "dce_0_0", .id = DSC_0,
-               .base = 0x80000, .len = 0x29c,
+               .base = 0x80000, .len = 0x4,
                .features = BIT(DPU_DSC_HW_REV_1_2),
                .sblk = &dsc_sblk_0,
        }, {
                .name = "dce_0_1", .id = DSC_1,
-               .base = 0x80000, .len = 0x29c,
+               .base = 0x80000, .len = 0x4,
                .features = BIT(DPU_DSC_HW_REV_1_2),
                .sblk = &dsc_sblk_1,
        }, {
                .name = "dce_1_0", .id = DSC_2,
-               .base = 0x81000, .len = 0x29c,
+               .base = 0x81000, .len = 0x4,
                .features = BIT(DPU_DSC_HW_REV_1_2) | BIT(DPU_DSC_NATIVE_42x_EN),
                .sblk = &dsc_sblk_0,
        }, {
                .name = "dce_1_1", .id = DSC_3,
-               .base = 0x81000, .len = 0x29c,
+               .base = 0x81000, .len = 0x4,
                .features = BIT(DPU_DSC_HW_REV_1_2) | BIT(DPU_DSC_NATIVE_42x_EN),
                .sblk = &dsc_sblk_1,
        },
index 2bf9f34e54c64ffdc26d053d130a81606c5d4a60..3b5061c4402a671690249e3abdf72d3326350b13 100644 (file)
@@ -163,7 +163,7 @@ static const struct dpu_pingpong_cfg sc7280_pp[] = {
 static const struct dpu_dsc_cfg sc7280_dsc[] = {
        {
                .name = "dce_0_0", .id = DSC_0,
-               .base = 0x80000, .len = 0x29c,
+               .base = 0x80000, .len = 0x4,
                .features = BIT(DPU_DSC_HW_REV_1_2) | BIT(DPU_DSC_NATIVE_42x_EN),
                .sblk = &dsc_sblk_0,
        },
index ccd0477f48774657eab322a4997788077dad79af..58f5e25679b15355f1f97f2b6ece886e277c96d9 100644 (file)
@@ -286,32 +286,32 @@ static const struct dpu_merge_3d_cfg sc8280xp_merge_3d[] = {
 static const struct dpu_dsc_cfg sc8280xp_dsc[] = {
        {
                .name = "dce_0_0", .id = DSC_0,
-               .base = 0x80000, .len = 0x29c,
+               .base = 0x80000, .len = 0x4,
                .features = BIT(DPU_DSC_HW_REV_1_2),
                .sblk = &dsc_sblk_0,
        }, {
                .name = "dce_0_1", .id = DSC_1,
-               .base = 0x80000, .len = 0x29c,
+               .base = 0x80000, .len = 0x4,
                .features = BIT(DPU_DSC_HW_REV_1_2),
                .sblk = &dsc_sblk_1,
        }, {
                .name = "dce_1_0", .id = DSC_2,
-               .base = 0x81000, .len = 0x29c,
+               .base = 0x81000, .len = 0x4,
                .features = BIT(DPU_DSC_HW_REV_1_2) | BIT(DPU_DSC_NATIVE_42x_EN),
                .sblk = &dsc_sblk_0,
        }, {
                .name = "dce_1_1", .id = DSC_3,
-               .base = 0x81000, .len = 0x29c,
+               .base = 0x81000, .len = 0x4,
                .features = BIT(DPU_DSC_HW_REV_1_2) | BIT(DPU_DSC_NATIVE_42x_EN),
                .sblk = &dsc_sblk_1,
        }, {
                .name = "dce_2_0", .id = DSC_4,
-               .base = 0x82000, .len = 0x29c,
+               .base = 0x82000, .len = 0x4,
                .features = BIT(DPU_DSC_HW_REV_1_2),
                .sblk = &dsc_sblk_0,
        }, {
                .name = "dce_2_1", .id = DSC_5,
-               .base = 0x82000, .len = 0x29c,
+               .base = 0x82000, .len = 0x4,
                .features = BIT(DPU_DSC_HW_REV_1_2),
                .sblk = &dsc_sblk_1,
        },
index 2b2e9d4800f8c368b065c0bf094ca6cbe5e2ea64..1b12178dfbcab7f2a365d66fc4386df79886b59a 100644 (file)
@@ -305,22 +305,22 @@ static const struct dpu_merge_3d_cfg sm8450_merge_3d[] = {
 static const struct dpu_dsc_cfg sm8450_dsc[] = {
        {
                .name = "dce_0_0", .id = DSC_0,
-               .base = 0x80000, .len = 0x29c,
+               .base = 0x80000, .len = 0x4,
                .features = BIT(DPU_DSC_HW_REV_1_2),
                .sblk = &dsc_sblk_0,
        }, {
                .name = "dce_0_1", .id = DSC_1,
-               .base = 0x80000, .len = 0x29c,
+               .base = 0x80000, .len = 0x4,
                .features = BIT(DPU_DSC_HW_REV_1_2),
                .sblk = &dsc_sblk_1,
        }, {
                .name = "dce_1_0", .id = DSC_2,
-               .base = 0x81000, .len = 0x29c,
+               .base = 0x81000, .len = 0x4,
                .features = BIT(DPU_DSC_HW_REV_1_2) | BIT(DPU_DSC_NATIVE_42x_EN),
                .sblk = &dsc_sblk_0,
        }, {
                .name = "dce_1_1", .id = DSC_3,
-               .base = 0x81000, .len = 0x29c,
+               .base = 0x81000, .len = 0x4,
                .features = BIT(DPU_DSC_HW_REV_1_2) | BIT(DPU_DSC_NATIVE_42x_EN),
                .sblk = &dsc_sblk_1,
        },
index c43bda0bc7082280cfd2c263523cd069660dbd80..7bed819dfc390235953838649148135845667298 100644 (file)
@@ -320,22 +320,22 @@ static const struct dpu_merge_3d_cfg sm8550_merge_3d[] = {
 static const struct dpu_dsc_cfg sm8550_dsc[] = {
        {
                .name = "dce_0_0", .id = DSC_0,
-               .base = 0x80000, .len = 0x29c,
+               .base = 0x80000, .len = 0x4,
                .features = BIT(DPU_DSC_HW_REV_1_2),
                .sblk = &dsc_sblk_0,
        }, {
                .name = "dce_0_1", .id = DSC_1,
-               .base = 0x80000, .len = 0x29c,
+               .base = 0x80000, .len = 0x4,
                .features = BIT(DPU_DSC_HW_REV_1_2),
                .sblk = &dsc_sblk_1,
        }, {
                .name = "dce_1_0", .id = DSC_2,
-               .base = 0x81000, .len = 0x29c,
+               .base = 0x81000, .len = 0x4,
                .features = BIT(DPU_DSC_HW_REV_1_2) | BIT(DPU_DSC_NATIVE_42x_EN),
                .sblk = &dsc_sblk_0,
        }, {
                .name = "dce_1_1", .id = DSC_3,
-               .base = 0x81000, .len = 0x29c,
+               .base = 0x81000, .len = 0x4,
                .features = BIT(DPU_DSC_HW_REV_1_2) | BIT(DPU_DSC_NATIVE_42x_EN),
                .sblk = &dsc_sblk_1,
        },