drm/amd/display: Add plane capabilities to dc_caps

[Why]
The current dc_caps doesn't provide the information needed to
determine the count and type of each plane to be exposed to userspace.

There are three types of DRM planes that are exposed to userspace:

1. Primary planes (can be used for modesetting)
2. Overlay planes (can be blended below or above a primary plane)
3. Cursor planes (blended topmost)

We need to know the number and type of each in amdgpu_dm to expose
to userspace.

Hardware supports blending planes below, above or both ways depending
on the ASIC. Alpha support is also ASIC dependent. Some hardware has
dedicated pipes for overlays and other hardware combines the pipes.

All of this should be exposed in a way that DM can query and use.

[How]
Introduce the dc_plane_cap structure that describes the capabilities
for the hw planes.

It describes:
- the type of the plane
- whether the plane can blend with planes below it
- whether the plane can blend with planes above it
- whether the plane supports per pixel alpha blending
- supported formats on the plane (partial list for now)

Pre DCN ASICs don't have their full capabilities described for now.
They can be updated as needed in the future.

Signed-off-by: Nicholas Kazlauskas <nicholas.kazlauskas@amd.com>
Reviewed-by: Tony Cheng <Tony.Cheng@amd.com>
Acked-by: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

diff --git a/drivers/gpu/drm/amd/display/dc/dc.h b/drivers/gpu/drm/amd/display/dc/dc.h
index ebd407384a04ecb32a37eaa3a424a20d6b01933c..ae60c62a2e2dfdf42caa3777263f1766019cca9e 100644 (file)
--- a/drivers/gpu/drm/amd/display/dc/dc.h
+++ b/drivers/gpu/drm/amd/display/dc/dc.h
@@ -42,6 +42,7 @@
 #define DC_VER "3.2.19"
 
 #define MAX_SURFACES 3
+#define MAX_PLANES 6
 #define MAX_STREAMS 6
 #define MAX_SINKS_PER_LINK 4
 
@@ -53,6 +54,22 @@ struct dc_versions {
        struct dmcu_version dmcu_version;
 };
 
+enum dc_plane_type {
+       DC_PLANE_TYPE_INVALID,
+       DC_PLANE_TYPE_DCE_RGB,
+       DC_PLANE_TYPE_DCE_UNDERLAY,
+       DC_PLANE_TYPE_DCN_UNIVERSAL,
+};
+
+struct dc_plane_cap {
+       enum dc_plane_type type;
+       uint32_t blends_with_above : 1;
+       uint32_t blends_with_below : 1;
+       uint32_t per_pixel_alpha : 1;
+       uint32_t supports_argb8888 : 1;
+       uint32_t supports_nv12 : 1;
+};
+
 struct dc_caps {
        uint32_t max_streams;
        uint32_t max_links;
@@ -73,6 +90,7 @@ struct dc_caps {
        bool force_dp_tps4_for_cp2520;
        bool disable_dp_clk_share;
        bool psp_setup_panel_mode;
+       struct dc_plane_cap planes[MAX_PLANES];
 };
 
 struct dc_dcc_surface_param {

diff --git a/drivers/gpu/drm/amd/display/dc/dce100/dce100_resource.c b/drivers/gpu/drm/amd/display/dc/dce100/dce100_resource.c
index 23044e6723e88311c8059d2d18dc19c58821b834..b733dc17db87f3d23eed6c3f1c1909077693479e 100644 (file)
--- a/drivers/gpu/drm/amd/display/dc/dce100/dce100_resource.c
+++ b/drivers/gpu/drm/amd/display/dc/dce100/dce100_resource.c
@@ -378,6 +378,11 @@ static const struct resource_caps res_cap = {
        .num_ddc = 6,
 };
 
+static const struct dc_plane_cap plane_cap = {
+       .type = DC_PLANE_TYPE_DCE_RGB,
+       .supports_argb8888 = true,
+};
+
 #define CTX  ctx
 #define REG(reg) mm ## reg
 
@@ -1023,6 +1028,9 @@ static bool construct(
 
        dc->caps.max_planes =  pool->base.pipe_count;
 
+       for (i = 0; i < dc->caps.max_planes; ++i)
+               dc->caps.planes[i] = plane_cap;
+
        if (!resource_construct(num_virtual_links, dc, &pool->base,
                        &res_create_funcs))
                goto res_create_fail;

diff --git a/drivers/gpu/drm/amd/display/dc/dce110/dce110_resource.c b/drivers/gpu/drm/amd/display/dc/dce110/dce110_resource.c
index 7549adaa1542beb28ce8087ed3dd73ff6ab6a33f..50af7e17db3b8573da134adf4adc9dd344b2256c 100644 (file)
--- a/drivers/gpu/drm/amd/display/dc/dce110/dce110_resource.c
+++ b/drivers/gpu/drm/amd/display/dc/dce110/dce110_resource.c
@@ -392,6 +392,21 @@ static const struct resource_caps stoney_resource_cap = {
                .num_ddc = 3,
 };
 
+static const struct dc_plane_cap plane_cap = {
+               .type = DC_PLANE_TYPE_DCE_RGB,
+               .blends_with_below = true,
+               .blends_with_above = true,
+               .per_pixel_alpha = 1,
+               .supports_argb8888 = true,
+};
+
+static const struct dc_plane_cap underlay_plane_cap = {
+               .type = DC_PLANE_TYPE_DCE_UNDERLAY,
+               .blends_with_above = true,
+               .per_pixel_alpha = 1,
+               .supports_nv12 = true
+};
+
 #define CTX  ctx
 #define REG(reg) mm ## reg
 
@@ -1371,6 +1386,11 @@ static bool construct(
 
        dc->caps.max_planes =  pool->base.pipe_count;
 
+       for (i = 0; i < pool->base.underlay_pipe_index; ++i)
+               dc->caps.planes[i] = plane_cap;
+
+       dc->caps.planes[pool->base.underlay_pipe_index] = underlay_plane_cap;
+
        bw_calcs_init(dc->bw_dceip, dc->bw_vbios, dc->ctx->asic_id);
 
        bw_calcs_data_update_from_pplib(dc);

diff --git a/drivers/gpu/drm/amd/display/dc/dce112/dce112_resource.c b/drivers/gpu/drm/amd/display/dc/dce112/dce112_resource.c
index ea3065d633722bf6b1f2199e5b44eba055646460..188fc992e94173c032362c93599865b7b18c5862 100644 (file)
--- a/drivers/gpu/drm/amd/display/dc/dce112/dce112_resource.c
+++ b/drivers/gpu/drm/amd/display/dc/dce112/dce112_resource.c
@@ -397,6 +397,11 @@ static const struct resource_caps polaris_11_resource_cap = {
                .num_ddc = 5,
 };
 
+static const struct dc_plane_cap plane_cap = {
+       .type = DC_PLANE_TYPE_DCE_RGB,
+       .supports_argb8888 = true,
+};
+
 #define CTX  ctx
 #define REG(reg) mm ## reg
 
@@ -1310,6 +1315,9 @@ static bool construct(
 
        dc->caps.max_planes =  pool->base.pipe_count;
 
+       for (i = 0; i < dc->caps.max_planes; ++i)
+               dc->caps.planes[i] = plane_cap;
+
        /* Create hardware sequencer */
        dce112_hw_sequencer_construct(dc);
 

diff --git a/drivers/gpu/drm/amd/display/dc/dce120/dce120_resource.c b/drivers/gpu/drm/amd/display/dc/dce120/dce120_resource.c
index 312a0aebf91fab31d8d4a6f6e076b5ed3aaf3c9a..01ea503faa12c2ba94b20513d9b5faf7bcd75c7e 100644 (file)
--- a/drivers/gpu/drm/amd/display/dc/dce120/dce120_resource.c
+++ b/drivers/gpu/drm/amd/display/dc/dce120/dce120_resource.c
@@ -454,6 +454,11 @@ static const struct resource_caps res_cap = {
                .num_ddc = 6,
 };
 
+static const struct dc_plane_cap plane_cap = {
+       .type = DC_PLANE_TYPE_DCE_RGB,
+       .supports_argb8888 = true,
+};
+
 static const struct dc_debug_options debug_defaults = {
                .disable_clock_gate = true,
 };
@@ -1171,6 +1176,9 @@ static bool construct(
 
        dc->caps.max_planes =  pool->base.pipe_count;
 
+       for (i = 0; i < dc->caps.max_planes; ++i)
+               dc->caps.planes[i] = plane_cap;
+
        bw_calcs_init(dc->bw_dceip, dc->bw_vbios, dc->ctx->asic_id);
 
        bw_calcs_data_update_from_pplib(dc);

diff --git a/drivers/gpu/drm/amd/display/dc/dce80/dce80_resource.c b/drivers/gpu/drm/amd/display/dc/dce80/dce80_resource.c
index 2eca81b5cf2f770cc08bba6eecb27d9d2afdff90..549855eb053f3ab6030580a9a4328a639a2de3a7 100644 (file)
--- a/drivers/gpu/drm/amd/display/dc/dce80/dce80_resource.c
+++ b/drivers/gpu/drm/amd/display/dc/dce80/dce80_resource.c
@@ -387,6 +387,11 @@ static const struct resource_caps res_cap_83 = {
                .num_ddc = 2,
 };
 
+static const struct dc_plane_cap plane_cap = {
+       .type = DC_PLANE_TYPE_DCE_RGB,
+       .supports_argb8888 = true,
+};
+
 static const struct dce_dmcu_registers dmcu_regs = {
                DMCU_DCE80_REG_LIST()
 };
@@ -1019,6 +1024,10 @@ static bool dce80_construct(
        }
 
        dc->caps.max_planes =  pool->base.pipe_count;
+
+       for (i = 0; i < dc->caps.max_planes; ++i)
+               dc->caps.planes[i] = plane_cap;
+
        dc->caps.disable_dp_clk_share = true;
 
        if (!resource_construct(num_virtual_links, dc, &pool->base,
@@ -1224,6 +1233,10 @@ static bool dce81_construct(
        }
 
        dc->caps.max_planes =  pool->base.pipe_count;
+
+       for (i = 0; i < dc->caps.max_planes; ++i)
+               dc->caps.planes[i] = plane_cap;
+
        dc->caps.disable_dp_clk_share = true;
 
        if (!resource_construct(num_virtual_links, dc, &pool->base,
@@ -1425,6 +1438,10 @@ static bool dce83_construct(
        }
 
        dc->caps.max_planes =  pool->base.pipe_count;
+
+       for (i = 0; i < dc->caps.max_planes; ++i)
+               dc->caps.planes[i] = plane_cap;
+
        dc->caps.disable_dp_clk_share = true;
 
        if (!resource_construct(num_virtual_links, dc, &pool->base,

diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_resource.c b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_resource.c
index dd8d189d17c930a038a2b8a2f5aaa520481d141e..9f1a009b19ee2c1e8e7c4a87e5d9ccf371b9223e 100644 (file)
--- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_resource.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_resource.c
@@ -516,6 +516,15 @@ static const struct resource_caps rv2_res_cap = {
 };
 #endif
 
+static const struct dc_plane_cap plane_cap = {
+       .type = DC_PLANE_TYPE_DCN_UNIVERSAL,
+       .blends_with_above = true,
+       .blends_with_below = true,
+       .per_pixel_alpha = true,
+       .supports_argb8888 = true,
+       .supports_nv12 = true
+};
+
 static const struct dc_debug_options debug_defaults_drv = {
                .sanity_checks = true,
                .disable_dmcu = true,
@@ -1510,6 +1519,9 @@ static bool construct(
        dcn10_hw_sequencer_construct(dc);
        dc->caps.max_planes =  pool->base.pipe_count;
 
+       for (i = 0; i < dc->caps.max_planes; ++i)
+               dc->caps.planes[i] = plane_cap;
+
        dc->cap_funcs = cap_funcs;
 
        return true;