parisc/unaligned: Rewrite 64-bit inline assembly of emulate_ldd()

Convert to use real temp variables instead of clobbering processor
registers. This aligns the 64-bit inline assembly code with the 32-bit
assembly code which was rewritten with commit 427c1073a2a1
("parisc/unaligned: Rewrite 32-bit inline assembly of emulate_ldd()").

While at it, fix comment in 32-bit rewrite code. Temporary variables are
now used for both 32-bit and 64-bit code, so move their declarations
to the function header.

No functional change intended.

Signed-off-by: Guenter Roeck <linux@roeck-us.net>
Cc: stable@vger.kernel.org # v6.0+
Signed-off-by: Helge Deller <deller@gmx.de>

diff --git a/arch/parisc/kernel/unaligned.c b/arch/parisc/kernel/unaligned.c
index 95a2741f26f3ed016185eb7558f5b1da5a0ca9fb..71e596ca5a86b04b78059718187943cbbff735f5 100644 (file)
--- a/arch/parisc/kernel/unaligned.c
+++ b/arch/parisc/kernel/unaligned.c
@@ -169,6 +169,7 @@ static int emulate_ldw(struct pt_regs *regs, int toreg, int flop)
 static int emulate_ldd(struct pt_regs *regs, int toreg, int flop)
 {
        unsigned long saddr = regs->ior;
+       unsigned long shift, temp1;
        __u64 val = 0;
        ASM_EXCEPTIONTABLE_VAR(ret);
 
@@ -180,25 +181,22 @@ static int emulate_ldd(struct pt_regs *regs, int toreg, int flop)
 
 #ifdef CONFIG_64BIT
        __asm__ __volatile__  (
-"      depd,z  %3,60,3,%%r19\n"                /* r19=(ofs&7)*8 */
-"      mtsp    %4, %%sr1\n"
-"      depd    %%r0,63,3,%3\n"
-"1:    ldd     0(%%sr1,%3),%0\n"
-"2:    ldd     8(%%sr1,%3),%%r20\n"
-"      subi    64,%%r19,%%r19\n"
-"      mtsar   %%r19\n"
-"      shrpd   %0,%%r20,%%sar,%0\n"
+"      depd,z  %2,60,3,%3\n"           /* shift=(ofs&7)*8 */
+"      mtsp    %5, %%sr1\n"
+"      depd    %%r0,63,3,%2\n"
+"1:    ldd     0(%%sr1,%2),%0\n"
+"2:    ldd     8(%%sr1,%2),%4\n"
+"      subi    64,%3,%3\n"
+"      mtsar   %3\n"
+"      shrpd   %0,%4,%%sar,%0\n"
 "3:    \n"
        ASM_EXCEPTIONTABLE_ENTRY_EFAULT(1b, 3b, "%1")
        ASM_EXCEPTIONTABLE_ENTRY_EFAULT(2b, 3b, "%1")
-       : "=r" (val), "+r" (ret)
-       : "0" (val), "r" (saddr), "r" (regs->isr)
-       : "r19", "r20" );
+       : "+r" (val), "+r" (ret), "+r" (saddr), "=&r" (shift), "=&r" (temp1)
+       : "r" (regs->isr) );
 #else
-    {
-       unsigned long shift, temp1;
        __asm__ __volatile__  (
-"      zdep    %2,29,2,%3\n"           /* r19=(ofs&3)*8 */
+"      zdep    %2,29,2,%3\n"           /* shift=(ofs&3)*8 */
 "      mtsp    %5, %%sr1\n"
 "      dep     %%r0,31,2,%2\n"
 "1:    ldw     0(%%sr1,%2),%0\n"
@@ -214,7 +212,6 @@ static int emulate_ldd(struct pt_regs *regs, int toreg, int flop)
        ASM_EXCEPTIONTABLE_ENTRY_EFAULT(3b, 4b, "%1")
        : "+r" (val), "+r" (ret), "+r" (saddr), "=&r" (shift), "=&r" (temp1)
        : "r" (regs->isr) );
-    }
 #endif
 
        DPRINTF("val = 0x%llx\n", val);