clk: qcom: ipq8074: drop the CLK_SET_RATE_PARENT flag from PLL clocks

GPLL, NSS crypto PLL clock rates are fixed and shouldn't be scaled based
on the request from dependent clocks. Doing so will result in the
unexpected behaviour. So drop the CLK_SET_RATE_PARENT flag from the PLL
clocks.

Cc: stable@vger.kernel.org
Fixes: b8e7e519625f ("clk: qcom: ipq8074: add remaining PLL’s")
Signed-off-by: Kathiravan Thirumoorthy <quic_kathirav@quicinc.com>
Link: https://lore.kernel.org/r/20230913-gpll_cleanup-v2-1-c8ceb1a37680@quicinc.com
Signed-off-by: Bjorn Andersson <andersson@kernel.org>

diff --git a/drivers/clk/qcom/gcc-ipq8074.c b/drivers/clk/qcom/gcc-ipq8074.c
index 63ac2ced76bb9539d49ac690516c1cdd09b86638..b7faf12a511a16f786d81643a1f90296212886f2 100644 (file)
--- a/drivers/clk/qcom/gcc-ipq8074.c
+++ b/drivers/clk/qcom/gcc-ipq8074.c
@@ -75,7 +75,6 @@ static struct clk_fixed_factor gpll0_out_main_div2 = {
                                &gpll0_main.clkr.hw },
                .num_parents = 1,
                .ops = &clk_fixed_factor_ops,
-               .flags = CLK_SET_RATE_PARENT,
        },
 };
 
@@ -121,7 +120,6 @@ static struct clk_alpha_pll_postdiv gpll2 = {
                                &gpll2_main.clkr.hw },
                .num_parents = 1,
                .ops = &clk_alpha_pll_postdiv_ro_ops,
-               .flags = CLK_SET_RATE_PARENT,
        },
 };
 
@@ -154,7 +152,6 @@ static struct clk_alpha_pll_postdiv gpll4 = {
                                &gpll4_main.clkr.hw },
                .num_parents = 1,
                .ops = &clk_alpha_pll_postdiv_ro_ops,
-               .flags = CLK_SET_RATE_PARENT,
        },
 };
 
@@ -188,7 +185,6 @@ static struct clk_alpha_pll_postdiv gpll6 = {
                                &gpll6_main.clkr.hw },
                .num_parents = 1,
                .ops = &clk_alpha_pll_postdiv_ro_ops,
-               .flags = CLK_SET_RATE_PARENT,
        },
 };
 
@@ -201,7 +197,6 @@ static struct clk_fixed_factor gpll6_out_main_div2 = {
                                &gpll6_main.clkr.hw },
                .num_parents = 1,
                .ops = &clk_fixed_factor_ops,
-               .flags = CLK_SET_RATE_PARENT,
        },
 };
 
@@ -266,7 +261,6 @@ static struct clk_alpha_pll_postdiv nss_crypto_pll = {
                                &nss_crypto_pll_main.clkr.hw },
                .num_parents = 1,
                .ops = &clk_alpha_pll_postdiv_ro_ops,
-               .flags = CLK_SET_RATE_PARENT,
        },
 };