media: hantro: vp9: use double buffering if needed
authorJernej Skrabec <jernej.skrabec@gmail.com>
Mon, 29 Nov 2021 18:26:27 +0000 (19:26 +0100)
committerMauro Carvalho Chehab <mchehab@kernel.org>
Thu, 16 Dec 2021 19:54:54 +0000 (20:54 +0100)
Some G2 variants need double buffering to be enabled in order to work
correctly, like that found in Allwinner H6 SoC.

Add platform quirk for that.

Reviewed-by: Andrzej Pietrasiewicz <andrzej.p@collabora.com>
Signed-off-by: Jernej Skrabec <jernej.skrabec@gmail.com>
Signed-off-by: Hans Verkuil <hverkuil-cisco@xs4all.nl>
Signed-off-by: Mauro Carvalho Chehab <mchehab+huawei@kernel.org>
drivers/staging/media/hantro/hantro.h
drivers/staging/media/hantro/hantro_g2_regs.h
drivers/staging/media/hantro/hantro_g2_vp9_dec.c

index 33eb3e092cc165c5f5bc9a204dd1af86ca4c678c..d03824fa3222ca37eb38c2d9324f01739ccfd134 100644 (file)
@@ -73,6 +73,7 @@ struct hantro_irq {
  * @num_clocks:                        number of clocks in the array
  * @reg_names:                 array of register range names
  * @num_regs:                  number of register range names in the array
+ * @double_buffer:             core needs double buffering
  */
 struct hantro_variant {
        unsigned int enc_offset;
@@ -94,6 +95,7 @@ struct hantro_variant {
        int num_clocks;
        const char * const *reg_names;
        int num_regs;
+       unsigned int double_buffer : 1;
 };
 
 /**
index 9c857dd1ad9b30c952088a4122cf694f68d04a40..15a391a4650e60904372b6d13c8f1ddf571f42ac 100644 (file)
 #define g2_apf_threshold       G2_DEC_REG(55, 0, 0xffff)
 
 #define g2_clk_gate_e          G2_DEC_REG(58, 16, 0x1)
+#define g2_double_buffer_e     G2_DEC_REG(58, 15, 0x1)
 #define g2_buswidth            G2_DEC_REG(58, 8,  0x7)
 #define g2_max_burst           G2_DEC_REG(58, 0,  0xff)
 
index e04242d10fa2444e243c5ce3db3462d6e814024e..d4fc649a4da13b830bbeccf7697693305ba0597b 100644 (file)
@@ -847,6 +847,8 @@ config_registers(struct hantro_ctx *ctx, const struct v4l2_ctrl_vp9_frame *dec_p
        hantro_reg_write(ctx->dev, &g2_clk_gate_e, 1);
        hantro_reg_write(ctx->dev, &g2_max_cb_size, 6);
        hantro_reg_write(ctx->dev, &g2_min_cb_size, 3);
+       if (ctx->dev->variant->double_buffer)
+               hantro_reg_write(ctx->dev, &g2_double_buffer_e, 1);
 
        config_output(ctx, dst, dec_params);