arm64: dts: imx8ulp: add caam jr

Add crypto node in device tree for:
- CAAM job-ring

Signed-off-by: Varun Sethi <v.sethi@nxp.com>
Signed-off-by: Pankaj Gupta <pankaj.gupta@nxp.com>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>

diff --git a/arch/arm64/boot/dts/freescale/imx8ulp.dtsi b/arch/arm64/boot/dts/freescale/imx8ulp.dtsi
index cbed01bb8cc06fd8d30f82c5fa2690bc33699b05..e32d5afcf4a96218ad5fabeb20447a5b09beec1d 100644 (file)
--- a/arch/arm64/boot/dts/freescale/imx8ulp.dtsi
+++ b/arch/arm64/boot/dts/freescale/imx8ulp.dtsi
@@ -252,6 +252,38 @@
                                #reset-cells = <1>;
                        };
 
+                       crypto: crypto@292e0000 {
+                               compatible = "fsl,sec-v4.0";
+                               reg = <0x292e0000 0x10000>;
+                               ranges = <0 0x292e0000 0x10000>;
+                               #address-cells = <1>;
+                               #size-cells = <1>;
+
+                               sec_jr0: jr@1000 {
+                                       compatible = "fsl,sec-v4.0-job-ring";
+                                       reg = <0x1000 0x1000>;
+                                       interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>;
+                               };
+
+                               sec_jr1: jr@2000 {
+                                       compatible = "fsl,sec-v4.0-job-ring";
+                                       reg = <0x2000 0x1000>;
+                                       interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>;
+                               };
+
+                               sec_jr2: jr@3000 {
+                                       compatible = "fsl,sec-v4.0-job-ring";
+                                       reg = <0x3000 0x1000>;
+                                       interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>;
+                               };
+
+                               sec_jr3: jr@4000 {
+                                       compatible = "fsl,sec-v4.0-job-ring";
+                                       reg = <0x4000 0x1000>;
+                                       interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>;
+                               };
+                       };
+
                        tpm5: tpm@29340000 {
                                compatible = "fsl,imx8ulp-tpm", "fsl,imx7ulp-tpm";
                                reg = <0x29340000 0x1000>;