arm64: dts: qcom: sc8280xp: Add PCIe bridge node

On Qcom SoCs, the PCIe host bridge is connected to a single PCIe bridge
for each controller instance. Hence, add a node to represent the bridge.

While at it, let's remove the bridge properties from board dts as they are
now redundant.

Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org>
Link: https://lore.kernel.org/r/20240321-pcie-qcom-bridge-dts-v2-9-1eb790c53e43@linaro.org
Signed-off-by: Bjorn Andersson <andersson@kernel.org>

diff --git a/arch/arm64/boot/dts/qcom/sc8280xp-lenovo-thinkpad-x13s.dts b/arch/arm64/boot/dts/qcom/sc8280xp-lenovo-thinkpad-x13s.dts
index 2806aa8ec497d5e17d56206def2755547fbdba39..f325066e24d862715d607d66d50dc5fdd5ec5aa5 100644 (file)
--- a/arch/arm64/boot/dts/qcom/sc8280xp-lenovo-thinkpad-x13s.dts
+++ b/arch/arm64/boot/dts/qcom/sc8280xp-lenovo-thinkpad-x13s.dts
@@ -733,22 +733,14 @@
        pinctrl-0 = <&pcie4_default>;
 
        status = "okay";
+};
 
-       pcie@0 {
-               device_type = "pci";
-               reg = <0x0 0x0 0x0 0x0 0x0>;
-               #address-cells = <3>;
-               #size-cells = <2>;
-               ranges;
-
-               bus-range = <0x01 0xff>;
-
-               wifi@0 {
-                       compatible = "pci17cb,1103";
-                       reg = <0x10000 0x0 0x0 0x0 0x0>;
+&pcie4_port0 {
+       wifi@0 {
+               compatible = "pci17cb,1103";
+               reg = <0x10000 0x0 0x0 0x0 0x0>;
 
-                       qcom,ath11k-calibration-variant = "LE_X13S";
-               };
+               qcom,ath11k-calibration-variant = "LE_X13S";
        };
 };
 

diff --git a/arch/arm64/boot/dts/qcom/sc8280xp.dtsi b/arch/arm64/boot/dts/qcom/sc8280xp.dtsi
index 4c77f69a24a798323baa079eb3f6bf9d1e748736..0403811264d8cfd3c5afec0c14bb86e8a78afd40 100644 (file)
--- a/arch/arm64/boot/dts/qcom/sc8280xp.dtsi
+++ b/arch/arm64/boot/dts/qcom/sc8280xp.dtsi
@@ -1803,6 +1803,16 @@
                        phy-names = "pciephy";
 
                        status = "disabled";
+
+                       pcie4_port0: pcie@0 {
+                               device_type = "pci";
+                               reg = <0x0 0x0 0x0 0x0 0x0>;
+                               bus-range = <0x01 0xff>;
+
+                               #address-cells = <3>;
+                               #size-cells = <2>;
+                               ranges;
+                       };
                };
 
                pcie4_phy: phy@1c06000 {
@@ -1904,6 +1914,16 @@
                        phy-names = "pciephy";
 
                        status = "disabled";
+
+                       pcie3b_port0: pcie@0 {
+                               device_type = "pci";
+                               reg = <0x0 0x0 0x0 0x0 0x0>;
+                               bus-range = <0x01 0xff>;
+
+                               #address-cells = <3>;
+                               #size-cells = <2>;
+                               ranges;
+                       };
                };
 
                pcie3b_phy: phy@1c0e000 {
@@ -2005,6 +2025,16 @@
                        phy-names = "pciephy";
 
                        status = "disabled";
+
+                       pcie3a_port0: pcie@0 {
+                               device_type = "pci";
+                               reg = <0x0 0x0 0x0 0x0 0x0>;
+                               bus-range = <0x01 0xff>;
+
+                               #address-cells = <3>;
+                               #size-cells = <2>;
+                               ranges;
+                       };
                };
 
                pcie3a_phy: phy@1c14000 {
@@ -2109,6 +2139,16 @@
                        phy-names = "pciephy";
 
                        status = "disabled";
+
+                       pcie2b_port0: pcie@0 {
+                               device_type = "pci";
+                               reg = <0x0 0x0 0x0 0x0 0x0>;
+                               bus-range = <0x01 0xff>;
+
+                               #address-cells = <3>;
+                               #size-cells = <2>;
+                               ranges;
+                       };
                };
 
                pcie2b_phy: phy@1c1e000 {
@@ -2210,6 +2250,16 @@
                        phy-names = "pciephy";
 
                        status = "disabled";
+
+                       pcie2a_port0: pcie@0 {
+                               device_type = "pci";
+                               reg = <0x0 0x0 0x0 0x0 0x0>;
+                               bus-range = <0x01 0xff>;
+
+                               #address-cells = <3>;
+                               #size-cells = <2>;
+                               ranges;
+                       };
                };
 
                pcie2a_phy: phy@1c24000 {