spi: axi-spi-engine: check for valid clock rate

This adds a check for a valid SCLK rate in the axi-spi-engine driver
during probe. A valid rate is required to get accurate timing for delays
and by not allowing 0 we can avoid divide by zero errors later without
additional checks.

Signed-off-by: David Lechner <dlechner@baylibre.com>
Link: https://lore.kernel.org/r/20231117-axi-spi-engine-series-1-v1-8-cc59db999b87@baylibre.com
Signed-off-by: Mark Brown <broonie@kernel.org>

diff --git a/drivers/spi/spi-axi-spi-engine.c b/drivers/spi/spi-axi-spi-engine.c
index 81974424695213922714d9d5b9b9649bad2b563f..8a6fbb3bb3f1ac84419c6f2c4702d6e8021121e8 100644 (file)
--- a/drivers/spi/spi-axi-spi-engine.c
+++ b/drivers/spi/spi-axi-spi-engine.c
@@ -532,6 +532,9 @@ static int spi_engine_probe(struct platform_device *pdev)
        host->transfer_one_message = spi_engine_transfer_one_message;
        host->num_chipselect = 8;
 
+       if (host->max_speed_hz == 0)
+               return dev_err_probe(&pdev->dev, -EINVAL, "spi_clk rate is 0");
+
        ret = devm_spi_register_controller(&pdev->dev, host);
        if (ret)
                return ret;